A recent patent from Apple, titled "Stacked Pixel Image Sensor with High Dynamic Range and Low Noise," highlights advancements in CMOS image sensor technology, focusing on high dynamic range (HDR) capabilities for mobile devices.
Stacked Architecture and Pixel Design
Traditional image sensors often use a 4T pixel structure with four transistors: transfer gate, reset gate, select gate, and source-follower. This design, built on a single CMOS process, enables correlated double sampling (CDS) to reduce fixed pattern noise (FPN) and thermal noise (kTC) by precisely controlling charge transfer.
Alternatively, a 3T pixel structure omits the transfer gate, reducing pixel size for higher density but increasing noise. Apple¡¯s patent employs a 3T pixel within a stacked architecture, integrating lateral overflow integration capacitor (LOFIC) and current storage circuits to achieve both high pixel density and low noise with enhanced dynamic range.
Two-Layer Stacked Design
Apple¡¯s sensor splits the CMOS into two chips:
- Sensor Chip (Top Layer): Optimized for light capture, containing photodiodes and LOFIC circuits.
- Logic Chip (Bottom Layer): Handles signal processing with current storage, column readout, and timing control circuits.
This separation allows each layer to use optimized fabrication processes, improving efficiency and enabling complex pixel-level circuits for noise reduction. The compact design suits space-constrained mobile devices.
LOFIC for Dynamic Range
LOFIC, already used in sensors from companies like OmniVision and SmartSens, manages light intensity by dynamically allocating charge across capacitors, preventing overexposure in bright scenes or underexposure in low light. Apple¡¯s multi-stage charge storage system includes:
- Low Light: Floating diffusion node for weak signals.
- Medium Light: A 20fF capacitor connected via a LOFIC transistor.
- High Light: A 500fF capacitor for intense light, linked through another LOFIC transistor.
This system captures a dynamic range up to 120dB (approximately 20 stops), surpassing the 17-stop range of professional cinema cameras like the ARRI ALEXA 35, enabling native HDR imaging without multi-frame synthesis.
Noise Reduction via Current Storage
Apple¡¯s current storage circuit, integrated per pixel on the logic chip, performs hardware-based noise reduction through a ¡°sample-subtract¡± process:
- First Readout: Captures signal plus noise (thermal and kTC).
- Reset and Noise Sampling: Resets the pixel and reads pure noise, stored in the circuit¡¯s capacitor.
- Noise Subtraction: CDS subtracts the stored noise from the initial readout in the analog domain.
This real-time, analog noise cancellation preserves image detail, delivering clean, low-noise images even in low-light conditions, outperforming AI-based noise reduction.
Manufacturing Challenges
Implementing this technology poses significant hurdles:
- Stacking Yield: Cu-Cu hybrid bonding and through-silicon vias (TSVs) require atomic-level precision, risking low yields and high costs.
- LOFIC Integration: Precise capacitor fabrication and leakage control within tiny pixels demand advanced lithography and deposition.
- Circuit Consistency: Ensuring uniform noise cancellation across millions of pixels is a design and fabrication challenge.
Industry Implications
Stacked architectures and LOFIC are already in use in automotive and industrial imaging, with companies like OmniVision, SmartSens, and Sony achieving mass production. Apple¡¯s patent suggests HDR is a key focus for mobile imaging, potentially driving significant advancements in image sensor technology over the next four to five years.
