Description

<style>.e_editor{font:14px/24px Arial,'microsoft yahei','Times New Roman','b8bf53';}.e_editor div,e_editor p,e_editor td,e_editor th,e_editor li{font-weight:inherit;font-size:inherit;font-style:inherit;font-family:inherit;}.e_editor ul{margin:-10px 0 20px;}.e_editor li{padding:5px 0;}.e_table{width:96%;border-collapse:collapse;empty-cells:show;}.e_table th,.e_table td{padding:5px;border:2px solid #eee;}.e_img{padding:10px 0;text-align:center;}.e_p{line-height:20px;padding:0 0 20px;text-indent:0em;}</style> <div class="e_editor"> <div class="e_p"> To help automate the interconnect process between bare die and a pc board, PowerBGA 3.0 provides flip chip design tools, support for design reuse methodologies with a new physical design reuse (PDR) module and expanded constraint-driven design capabilities. The enhancements reportedly enable packaging engineers to complete designs in less time with automatic layout of repetitive circuitry, enhanced to design intelligence and fewer design rule violation repairs. Enhanced flip chip support in the new version includes new functionality in the Component IQ, Library IQ and Design Editor modules. These enhancements ensure accuracy and allow engineers to specify requirements early in the design process. The PDR module eliminates the need for time-consuming recreation of design elements by allowing users to reuse circuitry while maintaining the physical integrity of the layout. </div> </div>