Description

<span style="font-family:&quot;font-size:16px;">It is well learnt that</span><strong><span style="font-family:&quot;font-size:16px;"> isometric drawing </span></strong><span style="font-family:&quot;font-size:16px;">is widely required for high-speed boards, and it turns out quite strange if the drawing is not applied during the whole </span><a href="https://www.allpcb.com/drilling_pcb_design.html" target="_blank"><span style="font-family:&quot;font-size:16px;">design</span></a><span style="font-family:&quot;font-size:16px;"> process. We have introduced some easy and fast method for isometric drawing in our previous essay, Allegro is widely used and popular for designers. You can refer to the below image. The drawings are neat, beautiful and tidy with same trace width.</span><br /> <p> <br /> </p> <p style="text-align:center;"> <img src="https://file.allpcb.com/bbs/19/01/03/144345354.jpg" alt="isometric drawing" /> </p> <br /> <p> <span style="font-family:&quot;font-size:16px;">Internal storage is popular in high-speed boards, which requires engineers to master PCB internal storage design, and learn to organize and classify variable signals. We get to know topology structure, how to do the </span><a href="https://www.allpcb.com/pcb_layout.html" target="_blank"><span style="font-family:&quot;font-size:16px;">layout</span></a><span style="font-family:&quot;font-size:16px;">, how to design the isometric drawing ect. Let’s take examples for DDR3.&nbsp;</span> </p> <p> <br /> </p> <p> <strong><span style="font-family:&quot;font-size:16px;">Layout：</span></strong> </p> <span style="font-family:&quot;font-size:16px;">1. Consider about the maintainability of </span><strong><span style="font-family:&quot;font-size:16px;">BGA</span></strong><span style="font-family:&quot;font-size:16px;">, the min. trace space around BGA component parts is 5MM, with min. BGA 3mm;</span><br /> <span style="font-family:&quot;font-size:16px;"> 2. DFM reliability: Per relative process requirement, the component space must meet the DFM requirement, and we have to consider about the beauty of the overall layout;</span><br /> <span style="font-family:&quot;font-size:16px;"> 3. If it is easy to meet absolute isometric drawing and relative length. We have to care about the length limitation and order requirement;</span><br /> <span style="font-family:&quot;font-size:16px;"> 4. The location of filter capacity and pull-up resistors: the capacity should be close to every PIN, while the capacitors scared around the IC, the resistors should be locate per the requirement, ( the layout length should be no more than 500mil).&nbsp;</span><br /> <p> <br /> </p> <p style="text-align:center;"> <img src="https://file.allpcb.com/bbs/19/01/03/144417903.jpg" alt="filter capacity" /> </p> <br /> <strong><span style="font-family:&quot;font-size:16px;">Layout：</span></strong><br /> <span style="font-family:&quot;font-size:16px;"> 1. Special </span><strong><span style="font-family:&quot;font-size:16px;">impedance control</span></strong><span style="font-family:&quot;font-size:16px;">: Single-end 5O ohm, differential 100ohm;</span><br /> <span style="font-family:&quot;font-size:16px;"> 2. Data wire is grouped every 11 pieces（D0~D7,DM0,DQS0+/-）,（D8~D15,DM1,DQS1+/-）the ground plane are considered as reference plane, no other signals inside;&nbsp;</span><br /> <span style="font-family:&quot;font-size:16px;"> 3. Try not to change layers for every signals, especially for data wire, no more than 2vias clock line, the signals space must meet 3W standards.</span><br /> <span style="font-family:&quot;font-size:16px;"> 4. Data trace, impedance control trace, clock trace space should be no less than 15MIL or 3W;</span><br /> <span style="font-family:&quot;font-size:16px;"> 5. All the signal trace should not be separated with complete reference plane, once there is layer change, please pay attention to increase the vias or decoupling capacitors;</span><br /> <span style="font-family:&quot;font-size:16px;"> 6. For Vref power plane, the recommended trace width should be no less than 15mil, and the space is no less than 20 mil for other signal traces.</span><br />