Description

<style>.e_editor{font:14px/24px Arial,'microsoft yahei','Times New Roman','b8bf53';}.e_editor div,e_editor p,e_editor td,e_editor th,e_editor li{font-weight:inherit;font-size:inherit;font-style:inherit;font-family:inherit;}.e_editor ul{margin:-10px 0 20px;}.e_editor li{padding:5px 0;}.e_table{width:96%;border-collapse:collapse;empty-cells:show;}.e_table th,.e_table td{padding:5px;border:2px solid #eee;}.e_img{padding:10px 0;text-align:center;}.e_p{line-height:20px;padding:0 0 20px;text-indent:0em;}</style> <div class="e_editor"> <div class="e_p"> This technical brief discusses thermal design techniques for IC packages—such as QFN, DFN, and MLP—that incorporate an exposed thermal pad. </div> <div class="e_p"> Most designers are by now quite familiar with integrated-circuit packages that incorporate an “exposed pad” or “thermal pad” in addition to the component’s power, ground, and signal connections. These thermal pads are associated with a variety of package abbreviations—QFN (quad flat no-lead), DFN (dual flat no-lead), MLF (micro leadframe), MLP (micro leadframe package), and LLP (leadless leadframe package), to name a few. </div> <div class="e_p"> A major advantage of thermal-pad packages is, not surprisingly, enhanced thermal performance. </div> <div class="e_p"> Inside the package is the semiconductor die, and this die contains the circuitry that generates heat during operation. Underneath the die (and attached to it) is the thermal pad; heat can readily flow from the die to the thermal pad, and thus the die can dissipate more power without exceeding the maximum junction temperature—assuming, of course, that the PCB designer has ensured that heat can readily flow from the thermal pad to the ambient environment. </div> <div class="e_p"> Proper thermal design for QFN packages is generally based on the use of vias in the portion of the PCB that is soldered to the thermal pad. A simpler approach, if you have plenty of available board space, is a large copper area that includes the connection to the thermal pad. Unfortunately, this is feasible only with dual-row packages. </div> <div class="e_p"> When your component has terminals on all four sides (as is often the case), your only option is vias. (By the way, the terminals are best referred to as “lands,” since the flat exposed metal on the underside of the package cannot accurately be described as a pin or a lead.) Vias conduct heat from the thermal pad to other <a href="https://www.allpcb.com/pcb/pcb_layers.html" target="_blank">PCB layers</a>, and from there to the surrounding environment. But a few questions arise: </div> <ul> <li> How many vias? </li> <li> What should the via-to-via spacing be? </li> <li> How do I ensure that the vias will not interfere with the soldering process? </li> </ul> <div class="e_p"> The number of vias will, of course, depend on the size of the thermal pad and how concerned you are about heat transfer. If you anticipate no high-temperature stress and no significant power consumption, you could forget the vias altogether and assume that the typical package-to-ambient thermal paths will be adequate. But the vias are helpful in most cases; they’re insurance in case you operate at higher power than initially expected, and they can help improve performance by keeping the part’s internal temperature more stable. </div> <div class="e_p"> The consensus among experts seems to be the following: vias should be spaced at a center-to-center pitch of approximately 1.2 mm, with a via diameter of 0.25 to 0.33 mm. </div> <div class="e_p"> If you want to maximize your thermal performance, the number of vias becomes a question of geometry—i.e., however many you can fit while maintaining the recommended size and spacing. </div> <div class="e_p"> No discussion of QFN layout would be complete without the issue of solder wicking. Capillary action draws molten solder into the vias, possibly leaving the component with insufficient solder or creating a solder bump on the other side of the PCB. </div> <div class="e_p"> You can mitigate the problem by using the smallest recommended via size, but the real solution is altering the via itself so as to obstruct solder flow. The options here, in order of increasing performance (and hence cost), are tenting, capping/plugging, and filling. A conversation with your PCB fab should help you decide which is best for your application. </div> </div>