What Is DRAM?
Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that stores data using electrical charge in capacitors. Each binary bit (0 or 1) is represented by the presence or absence of electrical charge in a capacitor.
The basic storage cell in DRAM consists of two components: a transistor and a capacitor. To store a bit, the transistor charges or discharges the capacitor. When a bit is read, the act of reading causes the charge to flow out of the capacitor.
DRAM vs. SRAM
Compared to Static RAM (SRAM), DRAM has a simpler structure. Each bit in DRAM requires only one capacitor and one transistor, while SRAM typically requires six transistors per bit. This allows DRAM to achieve much higher memory density and lower cost per unit of storage. However, SRAM is generally faster than DRAM.
Due to these advantages, DRAM is widely used in memory modules for laptops and desktop computers.
Why Does DRAM Require Refreshing?
A key characteristic of DRAM is that it must be refreshed regularly. This is due to the leakage of electrical charge from the capacitors used to store data. Over time, the stored charge diminishes, risking data loss.
To prevent this, DRAM performs periodic refresh operations. These refreshes are triggered by an internal timer that systematically reads and rewrites the data in the memory cells, restoring the charge in each capacitor and preserving the stored information.
Modern DRAM devices typically implement "self-refresh" functionality. This means the refresh process is managed internally by a dedicated control circuit, reducing the need for external management by the CPU or memory controller and improving system efficiency and reliability.
Types of Refresh Mechanisms
DRAM refresh operations are typically performed at the row level, with entire rows being refreshed in each cycle. There are several refresh methods, including:
- Distributed Refresh
- Burst (Concentrated) Refresh
- Asynchronous Refresh
These refresh strategies help maintain data integrity while balancing power consumption and performance.
