ALLPCB
Overview
This application note describes configuring the eZ80F91 microcontroller to communicate over an Ethernet cable. Data is transmitted from one eZ80F91 device to another and vice versa. A terminal emulator on a PC (for example, HyperTerminal or similar software) provides a user interface by displaying data received over Ethernet and sending data to the eZ80F91 device at the other end of the cable. The application discussed follows the IEEE 802.3 frame format.
EMAC and Interface
Zilog's eZ80F91 MCU includes an on-chip Ethernet Media Access Controller (EMAC) and a full-featured 10/100 Mbps Media Independent Interface (MII). The EMAC contains the following blocks:
- Central clock and reset module
- Host memory interface and transmit/receive arbitrator
- FIFO buffers and DMA control blocks for transmit and receive
- 802.3x media access control block
- MII management interface
Key MCU Features
- High-performance pipelined eZ80 CPU core with single-cycle instruction fetch
- 10/100 Base-T Ethernet Media Access Controller with Media Independent Interface (MII)
- 256 KB flash memory
- 16 KB SRAM (8 KB user and 8 KB dedicated to Ethernet)
- Low-power features including sleep and pause modes and selective peripheral power-down control
- Two universal asynchronous receiver/transmitters (UARTs) with independent baud rate generators
- Serial peripheral interface (SPI) with independent clock source
- I2C with independent clock source
- Infrared encoder/decoder compliant with IrDA
- Seamless external peripheral interface with four chip selects, independent wait-state generator, external WAIT input pin; supports Z80, Intel, and Motorola-style buses
- Fixed-priority vectored interrupts (internal and external) and interrupt controller
- Real-time clock with separate VDD pin for battery backup and optional on-chip 32 kHz oscillator or external 50/60 Hz input
- Four 16-bit counters/timers with prescalers and direct I/O drive
- Watchdog timer with internal oscillator option
- 32-bit general-purpose I/O
Computer Networks and Ethernet
Computer networks allow computers and other electronic devices to share information. The Internet is an example of a wide-area network connecting millions of computers worldwide. At a smaller scale, a local area network (LAN) connects devices that are close together, such as those within an office building. The primary architecture for LANs is Ethernet, which defines the physical and data link layers of the OSI model discussed below.
OSI Model
The Open Systems Interconnection (OSI) model specifies how network protocols and devices should communicate. It consists of seven layers arranged from top to bottom. The top three layers describe application-specific functions such as data formatting and connection management. Examples of protocols at the upper layers include Hypertext Transfer Protocol (HTTP) and Simple Mail Transfer Protocol (SMTP). The lower four layers describe network-specific functions such as addressing and routing. Examples at the lower layers include Transmission Control Protocol/Internet Protocol (TCP/IP) and Ethernet.
Ethernet IEEE 802.3 Frame Format
The Ethernet IEEE 802.3 frame defines the frame format at the physical and data link layers of the OSI model. The upper five OSI layers are represented within the data fields of an Ethernet frame.
System Block Diagram and Hardware Setup
Two eZ80F91 MCU development boards are connected using a crossover Ethernet cable. Each board is connected via an RS232 cable to a PC running a terminal emulator to provide a user interface. If a COM port is not available, the eZ80F910300KITG hardware can use a USB-to-serial cable instead of an RS232 cable. Figure 2 shows the connection block diagram used in this application. The application was developed and tested using Zilog development boards; the provided source code supports these boards and can be used on any of them in any combination.
