ALLPCB
Overview
Packaging integrates components into a multilayer printed circuit board structure. Smaller footprints, 3D packaging that allows stacking passive and active components, reduced parasitic effects, and improved thermal management have driven this development. Embedding components into substrate assemblies is not new and is mature for low-power and logic device packages. Examples of high-volume products using embedded PCB techniques include MicroSIP packaging (Texas Instruments and AT&S) and Infineon’s BLAD packaging.
Embedded construction and materials
Figure 1 shows a simplified cross section of a 10 kW inverter using IGBTs. In the described work, a 100 μm copper foil forms a substrate that connects to a heatsink. An electrically insulating but thermally conductive prepreg layer (4.8 W/mK) fills the vertical and horizontal gaps around a 400 μm copper region that serves as a leadframe for sintering chips. A thick (10–12 μm) copper layer covers the top of the chip; this is an additional process step compared with traditional aluminum top metallization. Copper electroplating fills laser-drilled vias. Top copper traces provide wiring and contacts and allow placement of additional components such as capacitors or controllers, similar to a conventional PCB. Combinations of thick and thin copper rails and variable via sizes can be used to optimize module performance.
Higher power density requires efficient heat removal and conduction. A limitation of embedded approaches is the low thermal conductivity of conventional FR-4 (~0.3 W/mK); carefully designed via patterns can mitigate this. The thickness of copper laminates and layers is critical: thicker layers support higher currents and dissipate heat more effectively but increase lateral heat spreading, which can affect adjacent embedded chips.
Mismatch in coefficients of thermal expansion (CTE) produces stress and can cause failures. Embedding on ceramic substrates such as aluminum nitride (AlN) with surrounding copper layers can provide better CTE matching to SiC while providing the required electrical isolation. Symmetric laminate stackups (top-to-bottom) also improve stress distribution and enable double-sided cooling.
Electrical layout and parasitics
Wide-bandgap devices enable high switching frequency and fast transition rates, so layouts must be optimized to reduce parasitic inductance. The power-loop inductance L_PL, including common-source inductance, is a major factor for switching losses, voltage overshoot, and conducted electromagnetic interference (EMI). Shielding switching nodes between external DC copper layers can reduce radiated EMI.
Examples of embedded PCB implementations with WBG devices
GaN Systems and AT&S developed the GaNpx packaging, an example of a low-inductance, small-footprint, low thermal resistance (Rthjc) package that uses GaN chips for 100 V and 650 V nodes and supports optional top or bottom cooling.
A Mitsubishi team demonstrated a 3D integrated SiC-based switching assembly. Two totem-pole SiC MOSFETs were embedded symmetrically within the PCB. A novel feature was a molded planar output inductor integrated around PCB windings using low-temperature epoxy. The gate driver was embedded near the switch. The design used four thick (400 μm) and four thin (35 μm) copper layers for high-current/thermal routes and fine-pitch routing for drivers. Compared with discrete TO-247 packages, the embedded devices showed improved RDS(on) across the temperature range, indicating improved electrical and thermal contact. Switching tests at 600 V and 30 A showed very small overshoot at dV/dt up to 58 kV/ns, confirming the low parasitic inductance advantage of 3D integration.
A collaborative team from Virginia Tech’s Center for Power Electronics Systems (CPES), an Austrian university, and AT&S implemented an embedded PCB power converter based on integrated gate-drive 1200 V SiC MOSFETs. AT&S’s embedded component packaging (ECP) was applied; CPES used a symmetric four-copper-layer embedded PCB stack to create half-bridge buck, boost, and AC-DC converters. Thermal resistance measurements showed excellent drain-side cooling with Rthjc ≈ 0.17 K/W. Simulation predicted a power-loop inductance of only 2.3 nH. In a quasi-square-wave buck converter that steps 800 V to 400 V at 25 A and 250 kHz switching, the VDS overshoot was 5.6 times lower than the same 1200 V SiC MOSFET in a discrete TO-247 package.
Infineon and Schweizer p2PACK approach
Infineon and Schweizer Electronic AG presented a 1200 V CoolSiC embedded PCB approach at PCIM 2023 based on Schweizer’s p2PACK embedding method. SiC MOSFETs were evaluated as a standard unit (S-unit) with top copper metallization to ease embedding. The method has been validated in production for 48 V MOSFETs with reported performance improvements. During embedding, S-units are placed into cutouts in the PCB laminate. Top and bottom copper vias and a surrounding copper frame provide low L_PL and low thermal resistance. Low thermal impedance is beneficial to limit temperature overshoot during fault events such as overcurrent.
Engineering samples of 1200 V, 11 mΩ CoolSiC S-cells and embedded half-bridge evaluation kits (enabling VIN up to 900 V and 50 kW without paralleling devices) have been demonstrated. Low L_PL ≈ 2 nH supports clean, fast switching. Preliminary switching results using a 1200 V, 14 mΩ embedded CoolSiC S-cell evaluation board showed that diode overshoot during conduction (referring to the body diode of the MOSFET in the OFF state) remained below 65 V for dV/dt > 90 V/ns.
Short-circuit behavior and protection
A key concern for low-inductance packages is current overshoot during short-circuit events. Infineon validated fast short-circuit detection at 800 V with detection times < 1 μs and demonstrated controlled behavior using various DESAT capacitor options.
Implications for automotive and other applications
Improvements in switching performance and thermal management can benefit automotive traction inverters and other high-power applications through higher efficiency. Other potential advantages include reduced system cost, flexibility for board-level design changes, smaller footprints for space-constrained applications, and simpler parallelization using scalable PCB embedding methods.
