NXP MCX A Series MCU Clock Architecture

The NXP MCX A series is designed for a broad range of general-purpose applications, offering a combination of low cost, low power consumption, high security, and reliability. The MCXA153, the first device in the series, was released in January 2024 for entry-level MCU applications. NXP plans to expand the MCX A series, providing a scalable upgrade path for hardware and software.

MCXA153 Clock Architecture

The clock architecture is divided into two main sections: clock source control and clock distribution.

Clock Source Control

Clock source control is handled by the System Clock Generator (SCG) and the VBAT module.

The SCG module provides the primary clock sources:

• FRO192M: A 192 MHz Free-Running Oscillator, configurable to 192, 96, 64, or 48 MHz. It also provides a dedicated 48 MHz output (clk_48m).
• FRO12M: A 12 MHz oscillator with an internal divider that can generate a 1 MHz clock (clk_1m).
• SOSC (System Oscillator): Supports an external crystal input from 8 MHz to 50 MHz.

The SCG module contains a clock multiplexer (Clock Mux) to select the source for the main system clocks: CPU_CLK, SYSTEM_CLK, and SLOW_CLK. The FRO192M, FRO12M, and SOSC outputs can also be routed directly to peripherals.

The VBAT module provides the 16.384 kHz FRO16K, which serves as a low-power clock source for low-power applications and can be used by the entire system or individual peripherals.

Clock Distribution

Clock distribution is managed by the Module Reset Clock Control (MRCC) module. The MRCC controls the CPU clock divider, which can scale the high-frequency source (e.g., 192 MHz from FRO192M) down to 96 MHz for the system clock. The SLOW_CLK is fixed at a divide-by-4 of the CPU_CLK.

The MRCC also includes a divider for the high-frequency FRO (fro_hf), which generates a lower-frequency `fro_hf_div` clock. This allows peripherals that do not require high speeds to use a slower clock, reducing overall system power consumption.

Peripherals receive their clocks via a multiplexer that selects from available sources, including `fro_hf_div`, `fro_hf`, `fro_12m`, and `clk_1m`. A final divider between the multiplexer and the peripheral scales the clock to the user-required frequency.

Comparison with the MCXN Series

The overall clock system architecture of the MCXA is similar to that of the MCXN series. The main difference is that the MCXA uses the MRCC, a submodule of SYSCON, to control clock multiplexer selection and division. Additionally, the MCXA153 does not include a Phase-Locked Loop (PLL) for clock multiplication.