How to Set Appropraite Hole Size During PCB Design

2019/1/23 16:01:25

Preparation for PCB Design


1. Accurate schematic diagram. Includes complete schematic and netlist, formal BOM with component encoding. The PCB package of all devices in the schematic (for components not included in the package library, the hardware engineer should provide a datasheet or a physical object and specify the order in which the pins are defined).


2. Provide basic information about the layout of the PCB or important units, the location of the core circuit, the location of the mounting holes, the components that need to be restricted, and the prohibited area.


Design Requirements


The designer must read the schematic diagram in detail, fully communicate with the project engineer, understand the circuit architecture, understand the working principle of the circuit, and clearly understand the layout and routing requirements of key signals.


Design Flow


1. PCB document specification

File naming rules: Use the numbering method to control the version of the PCB file. The file name is composed of: project code - board name - version number - date.



Project code: Internal numbering for different project projects, such as Anvi – AW, Longlun – SL, etc.Board name: Simple explanation in English. For example, the baseboard – mainboard, panel – panel, etc.The version number is unified by two, namely V10, V11, V30.... If there is a change in the schematic, the version upgrade changes the first digit, such as V10-V20; if it is only the layout change, the version upgrade changes the second digit, that is, V10-V11 and so on.



Date: Contains the year, month, and day in the format 20100108.

The entire code can only contain numbers and letters, connected by a dash.


Take the Anvi floor as an example, the file name is: AW-mainboard-v10-20100108


2. Determine the package of components

Open the netlist and browse through all the packages to ensure that all components are packaged correctly, especially the package size, pin order, aperture size and hole type and electrical properties (layer 25) must be consistent with the specifications on the datasheet , and the pad pins should be considered a little larger than the given size of the datasheet.


The package library and BOM of the component should be managed and maintained by a dedicated person to ensure uniform version.


3. Build a PCB frame

According to the customer's needs, determine the size of the frame and the location of the interface, as well as the installation holes, the forbidden area, the copper area and other related information.


4. Load the netlist

Load the netlist into the PCB and check the import report to ensure that all components are packaged correctly.


5. Stacking settings

Factors to consider when stacking settings:


Stable, low noise, low AC impedance PDS (Power Distribution System).

Transmission line structure requirements, microstrip line or strip line, whether there is a coating layer, etc.The characteristic impedance requirements of the transmission line.

Crosstalk noise suppression.Absorption and shielding of spatial electromagnetic interference.

The structure is symmetrical to prevent deformation. The wiring density determines the number of signal layers. The place with the highest wiring density is usually around the CPU. The number of pins on the CPU determines the number of signal layers that need to be used.


The thickness of the laminate and the thickness of the dielectric layer are determined by impedance control. Therefore, it is necessary to calculate the stacking parameters of 50 OHM single-ended impedance and 100 OHM differential impedance using simulation software (such as hyperlynx or SI9000) to determine the stack design.


Power and ground plane design: Try to design the power supply and the ground plane adjacent, and the thinner the dielectric between the power supply and the ground layer, the better, which can provide a good distribution of decoupling capacitors, which can greatly improve the system. Signal integrity and EMC form a stable, low noise and low AC impedance PDS. The ground plane should be placed on a layer directly adjacent to the PCB surface of the mounting component. The closer the ground plane is to the PCB main component surface (usually the surface layer), the lower the interconnect inductance will fall.


The lamination design also needs to take into account the warpage of the ply, that is, the lamination is designed to be vertically symmetrical.

The general rules for high speed digital design are:

Number of power layers + number of layers = number of signal layers

Power and ground are designed in pairs as much as possible, and at least one pair is a "back to back" design.

Straight line structure should be adopted as much as possible, and there is better EMC shielding. The key signal transmission should adopt symmetrical strip line structure (the specific electromagnetic field distribution can be viewed by 2D field solver, and hyperlynx also has this function).


6. Layout

First determine the origin and grids. It is recommended to use a 20 mil grid for layout and alignment.


The layout follows the principle of first and last, first big and then small. First divide the approximate location of each module, place the main IC device, and then place the decoupling capacitor. It is best to combine the IC and the corresponding decoupling capacitor as a UNION. Finally, peripheral circuit devices are laid. All components with positioning requirements are fixed and glued as required. Referring to the schematic diagram, other components are placed according to the flow pattern of the signal.


Note: For the placement of decoupling capacitors, the power supply terminal of the decoupling capacitor should share the same pad with the power supply pin of the IC, so that the distance between the IC and the decoupling capacitor is the smallest. The current preferably flows through the decoupling capacitor before the capacitor. Enter the power supply pin of the IC. If the decoupling capacitor and the IC power supply pin cannot share the pad, it is better to use a small copper surface instead of the trace between the IC and the decoupling capacitor to minimize the interconnection inductance of the decoupling capacitor.


When multiple decoupling capacitors with different capacitance values are used to decouple an IC, the decoupling capacitor with the smallest capacitance should be placed closest to the IC's power supply pin. Capacitors with large capacitance values can be placed slightly away from the IC due to the large decoupling radius.


The overall principle of the layout is: the total connection is as short as possible, the relevant device adopts the principle of proximity, and the key signal line is the shortest. Strong signals, weak signals, high voltage signals, and weak voltage signals are completely separated. The analog signal and the digital signal are separated. The spacing of the high frequency components should be sufficient to reduce nuisance.


1. Since the package size of the current component is not very standard, the product of each component manufacturer is very different. The design must have enough space to accommodate multiple supply situations.


2. For long and high components such as axial insertion on the PCB, horizontal installation should be considered to leave room for lying. Pay attention to the component hole position when lying down. The correct position is shown in the figure below.


3. The components of the metal shell, pay special attention to do not touch other components or printed conductors, leaving enough space. 4. Heavier components should be placed close to the PCB support points or sides to reduce PCB warpage. In particular, there are components such as BGAs on the PCB that cannot release deformation stress through the pins. This must be noted. 5, around the high-power components, around the heat sink, should not be placed with thermal elements, leaving enough distance. 6, the board connection, it is best not to lay components, so as not to damage the components when the board is divided.


The layout is optimized according to the standard of uniform distribution, balance of center of gravity, and aesthetics of the layout. The circuit parts of the same structure adopt a symmetrical layout as much as possible. Similar components are as uniform as possible in the X or Y direction for ease of production and commissioning.


Considering the need for soldering, inspection, testing, and mounting, the spacing between components should not be too close. It is recommended to design according to the following principles (where the gap refers to the gap between the different component pads and the smaller of the component body gap):


1. The gap between PLCC, QFP and SOP is ≥2.5 mm (100 mil).


2. The gap between PLCC, QFP, SOP and Chip and SOT is ≥1.5 mm (60 mil).


3. Chip, SOT Reflow gap between each other ≥ 0.3mm (12 mil), the gap of the wave soldering surface ≥ 0.8mm (32mil). It is important to note that if adjacent components on the wave soldering surface are staggered or highly inconsistent, the requirements of 10.3 c) are to be observed.


4. The gap between the BGA shape and other components is ≥5 mm (200 mil). If you do not consider repair, you can be as small as 2mm.




5. The gap between PLCC surface mount adapter and other components is ≥3 mm (120 mil).

BGA devices should first fan out the vias and dispense them, and then route them at each layer.


6. Set the via size type

Considering the overall layout and routing, choose the appropriate via size and type for the wiring. Unless it is used for space, signal integrity, and EMC requirements, such as mobile phone boards, blind and buried holes are not generally used. For the selection of through holes, the fan-out vias of the BGA are considered according to the ball pitch. For example, the fan-out hole of a BGA with a ball pitch of 0.8 mm usually selects a 10/18 mil through hole, and the other signal line vias usually select 12/24 mil. The power supply and ground vias can be selected according to the actual situation, but for the normalization requirements, the types of vias should not be too m

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