Low-Power Design for Embedded Systems

Introduction

Low-power design is a key consideration during product planning and design for embedded systems. Semiconductor performance has historically improved rapidly, but battery technology has lagged behind; for the same volume, battery capacity typically doubles on a much slower timescale. Increasing runtime and standby time requirements make it necessary to address low-power design across the whole system. Power control is a systems-level challenge that requires coordinated decisions on low-power component selection, hardware design and manufacturing, and software-level optimization. Based on project experience, this article summarizes key considerations for low-power design in embedded systems.

Low-Power Component Selection

Advances in semiconductor manufacturing and low-power architectures allow component choice to reduce system power from the outset.

1. Choose the main controller according to the target usage scenario. For compute-intensive applications, prefer controllers or SoCs with high energy efficiency. For example, Ambiq's Apollo series uses SPOT technology and can operate in the subthreshold region, reducing energy consumption by nearly 13x under certain conditions.
2. Power management ICs are critical for low-power designs. The quiescent power and conversion efficiency of regulators strongly affect battery life. Use low-quiescent-current LDOs or efficient DC-DC converters for low-power regulation; for example, some TPS7xx series regulators have quiescent currents around 1.2 uA.
3. Where possible, select external peripherals that provide trigger/output events rather than requiring polling. This allows the MCU to remain in sleep mode until an external interrupt wakes it, reducing active runtime.

Hardware Low-Power Design and Manufacturing

Hardware design decisions significantly influence system power consumption.

1. Control power to peripheral circuits with devices that support power-down. For peripherals not required during low-power modes, use MOSFET-based power switches controlled by the MCU to gate local power domains. Turn off these domains when they are not needed to reduce overall consumption.
2. Use multiple voltage rails. Voltage and power are closely related, so assigning different voltage levels to different modules can reduce power. Dynamic voltage and frequency scaling (DVFS) can lower module voltages and clock frequencies to the minimum required, reducing power in real time.
3. Minimize IO leakage. Configure MCU IO pins to defined default states (driven high or low) so they do not source or sink current when external peripherals are powered down. This avoids unintended leakage through IO lines.

Software Optimization for Power

Software optimization affects power consumption at multiple levels.

1. Reduce CPU clock frequency when possible. Lowering MCU clock speed reduces dynamic current; many devices exhibit a roughly linear relationship between operating frequency and power consumption because CMOS switching activity scales with clock rate.
2. Use MCU sleep modes effectively. When no tasks require CPU attention, enter low-power sleep. Instead of simply invoking sleep in an idle loop, implement an advanced sleep mechanism (for example, FreeRTOS tickless idle). Calculate the time until the next high-priority task is due and set the wake timer accordingly so the system stays in low power until that event.
3. Set GPIO states before sleep. Configure all GPIOs to defined levels prior to entering sleep to reduce leakage. Also ensure external sensors and peripherals are placed into low-power modes before MCU sleep.
4. Disable unused internal modules. In deep sleep modes, turn off clocks and power to internal modules that are not needed. Pay attention to analog blocks, which often consume significant power; disable AD/DA and other analog functions when not in use. SRAM retention also consumes current due to refresh; configure partial retention where supported to lower sleep power.
5. Configure radio/wireless parameters to reduce standby power. For example, with BLE devices, increasing advertising intervals reduces average standby current. Wireless stacks and chipsets often provide parameters (such as DTIM settings for Wi?Fi) that significantly affect idle current.

Conclusion

Achieving low power in embedded systems requires a comprehensive approach that considers components, hardware architecture, and software behavior. Careful analysis of usage scenarios, detailed attention to implementation details, and iterative evaluation of tradeoffs are necessary to optimize system power and extend battery life.