The evolution path for mainstream memory technology has been well established. From Fast Page (FP) mode and Extended Data Output (EDO) to SDR, DDR, and DDR2, each generation has brought advanced architectures, faster speeds, higher densities and bandwidth, along with lower supply voltages and reduced power consumption. These collective advancements have propelled DRAM and computing segments to new performance levels.
DRAM technology progress has coincided with the emergence of multi-core processors, new operating systems, and increasingly diverse requirements across computing platforms and applications¡ªincluding servers, workstations, mass storage systems, supercomputers, PCs, and peripherals. With each memory generation transition, memory considerations have grown more complex.
The DDR3 Transition
The shift to DDR3 follows this established pattern. By understanding the development history and trade-offs of main memory, designers can select high-performance memory devices that meet their platform, OS, and application requirements.
Before DDR technology emerged, SDR technology dominated. Prior to SDR, FP/EDO memory used asynchronous data transfer without clock signal references for data/address/command signals. SDR improved this by introducing a clock input as reference, with data transferred on the clock's rising edge (low-to-high transition).
The DRAM clock pin synchronization with system clocks enabled higher data rates than asynchronous memory.
Architectural Evolution
When DDR SDRAM launched in 2000, it doubled SDR data rates by transferring data on both rising and falling clock edges. DDR transfers 2 bits per clock cycle per data line (versus SDR's 1 bit).
This requires accessing 2 bits per data line from the memory array each clock cycle¡ªa process called 2n-prefetch (where clock cycle refers to the memory array's cycle time, operating at half the I/O buffer frequency and one-quarter the data rate). Prefetching enables evolutionary speed improvements while enhancing yield and performance.
DDR2 SDRAM functions similarly to DDR SDRAM but introduces features enabling faster speeds, while DDR3 builds upon DDR2's foundation.
DDR employs 2n-prefetch, DDR2 uses 4n-prefetch, and DDR3 implements 8n-prefetch. DDR3's internal data cycle time is one-eighth the external clock rate, with an internal data bus width eight times the external bus width. Each core clock cycle moves 8 bits per data line from memory array to I/O buffer.
Performance Enhancements
Additional bandwidth improvements include lower RTT (termination resistance) values to support higher data rates¡ªDDR2 starts at 50 ohms, while DDR3 begins at 20 ohms.
DDR3 delivers multiple technical improvements emphasizing faster speeds and enhanced performance. Devices are designed for high-speed signal transmission, with improved pinouts featuring additional power and ground balls for better power delivery.
Enhanced power/ground distribution combines with improved signal referencing to boost signal quality. DDR3's D/Q array reduces skew and tightens timing, while fully populated ball grids improve mechanical reliability.
With double DDR2's bandwidth, DDR3 speeds start where DDR2 peaks¡ªbeginning at 800Mbps and reaching 1,600Mbps. On a 64-bit bus, DDR3 achieves 6,400-12,800 Mtransfers/s.
Power Efficiency
DDR3 reduces supply voltage to 1.5V¡ªunder 20% lower than DDR2's standard 1.8V¡ªparticularly beneficial for mobile computing and other low-data-rate applications. The 15-20% power savings prove significant where efficiency outweighs raw performance, making DDR3 equally advantageous for notebook applications.
DDR3's 34-ohm drivers (versus DDR2's 18-ohm) are optimized for two-module-per-channel and point-to-point systems. DDR3 SDRAM drivers also benefit from reduced capacitance, dynamic On-Die Termination (ODT), and new calibration schemes.
The merged driver implementation reduces combined output driver/termination driver input capacitance by using shared pull-up/pull-down structures to enable multiple termination values¡ªa key DDR2 differentiator where separate structures handled output and termination impedance.
Key DDR3 Innovations
Dynamic ODT allows termination value optimization across load conditions, improving signal integrity while managing termination power. It enables seamless termination value changes between write commands to different modules¡ªa capability absent in DDR2 systems requiring bus idle time for such adjustments.
The new master reset feature eliminates unknown startup states, ensuring known initialization/recovery conditions while relieving controllers from preventing illegal commands. This resets all DDR3 memory device state information without individual register resets or power cycling, saving time and energy during cold or warm starts.
Application Outlook
DDR3 initially targets compute- and graphics-intensive applications like high-end desktop PCs and workstations that process massive datasets for realistic imaging. Its additive write latency scheme also boosts command bus efficiency in server applications.
DDR3 adoption is projected to grow in these segments, with notebook demand accelerating due to lower system power requirements.
