ALLPCB
Introduction
3D NAND represents an advanced limit in memory fabrication. Manufacturers such as Samsung, SK Hynix, Intel, and Yangtze Memory operate 3D NAND production lines, which reflect a country's chip-manufacturing capabilities. The following outlines the main fabrication steps for 3D NAND.
Key fabrication steps
- Substrate preparation: select 12-inch silicon wafers with a specified crystal orientation.
- Deposit alternating SiO2 and SiNx layers, each on the order of tens of nanometers. The number of layers varies by product; illustrations often show only a few layers, while real devices may have 64, 128, 400 layers or more.
- Deposit an amorphous silicon-carbon film to serve as a hard mask for channel etching.
- Pattern the hard mask to open etch windows for the stacked SiO2 and SiNx.
- Channel via-hole etch.
- Staircase etch.
- Deposit an amorphous silicon hard mask.
- Open the hard mask.
- Slit etch: etch the SiO2/SiNx stack into individual trenches.
- Etch away the SiNx in the stack and fill with TiN, tungsten (W), etc., i.e. w or d line fill process.
- Remove excess tungsten. To fill the channel vias, sequentially deposit a barrier oxide, charge-trap SiN, tunnel oxide, polysilicon, and core SiO2. The main functional stack is then completed.
- Deposit the dielectric layer and use CCP-RIE to etch contact holes.
- Fill the contact holes with metal and form the connecting metal lines (bit lines). This completes the main 3D NAND fabrication flow.
Many repetitive or minor steps have been omitted here; an actual process flow typically comprises several hundred individual steps.
