DDR4 Signal Integrity Test Overview

Test Scenarios

DDR4 signal testing falls into several scenarios:

1. Mobile devices with multiple stacked or closely placed package-on-board memory components. Because the controller and memory packages are adjacent and signals are not routed through vias, test points are not available on the board; testing requires an interposer.

1. Single-sided surface-mount packages (typical for TV applications). These can be tested with an interposer when available; otherwise the vias and solder resist can be scraped to access traces for probing. In some cases differential DQS traces on the top layer with 4 mil spacing are soldered as shown below.

1. UDIMM modules for PCs. These are the simplest case: single-sided memory modules expose signal vias on the back side that can be used as test points.

1. Server RDIMM and laptop SODIMM modules are typically double-sided and often require an interposer for full testing.

An alternative technique is to remove one memory package from the back side of an RDIMM and modify the SPD information to treat the module as single-sided. Although capacity is halved, signal testing is not affected and test points become available. For long motherboard routes this single-package removal has a negligible impact on branching; this method has been validated in practice.

Read/Write Waveform Separation

To separate read and write waveforms use single-shot triggering to capture a single read or write event. Read waveforms show DQS and DQ in phase. Write waveforms show DQS and DQ approximately 90 degrees out of phase.

After triggering a single event, stacked waveforms can be separated by:

1. Using the captured waveform and applying a visual/graphical trigger to select the general logic region (in or out). Keysight oscilloscopes support InfiniiScan for this purpose.
2. Examining single-shot read and write DQS patterns: the first two high/low pulse widths differ between read and write. Use the oscilloscope width(trigger) function to trigger on DQS.

Note 1: Tektronix Visual Trigger and Keysight InfiniiScan are licensed options that must be purchased separately; they are very effective for separating read and write events.

Note 2: The DDR3 method of using the direction of the preamble to separate read and write is ineffective for DDR4, since DDR4 preamble direction is not fixed and may be identical for read and write.

DDR4 Pin Descriptions

The following table summarizes common DDR4 pin functions.

Test Preparation

Recommended tools and consumables: soldering station, reballing board or temperature-controlled rework station, DDR device(s), tweezers, soldering iron, DDR adapter board, flux, desolder braid, solder balls. Test instrument used in this article: Tektronix DSA71254 12.5 GHz, 100 GS/s. Probes: P7313 (13 GHz x4) or P7513.

Test Items Overview

DDR testing typically covers:

• Timing measurements
• Ripple (power supply) measurements
• Signal integrity measurements, which include clock, command/address, write and read measurements

Component vendors often sample a subset of channels and signals rather than performing exhaustive tests. If resources permit, a full test can be performed by repeating the procedures for all DQ lines, though in most cases sampling a representative set of signals is sufficient.

Timing Measurements

Timing measurements cover items such as power-up/reset sequencing and various timing constraints. Examples include:

• VDD to RESET: after power-up, VDD high then RESET high. Requirement: minimum 200 us.
• RESET to CKE: after reset high, enable CKE. Requirement: minimum 500 us.
• tCKSRX: Clock stabilization to CKE enable. Requirement: min = max(5 nCK, 10 ns).

Power-down mode requires additional timing tests such as tPD (power-down entry) and tCKE. Example constraints:

• tPD: min tCKE(min), max 9*tREFI
• tCKE: min = max(3 nCK, 5 ns)
• tXP: min = max(3 nCK, 6 ns)
• tREFI: refresh interval varies with temperature

tRFC (self-refresh enable time): requirement min 260 ns.

When testing these timings use logic triggering with the appropriate logic pattern. In normal operation (not power-down), RESET and CKE should both remain high.

Ripple Measurements

Measure ripple on the following rails:

• VDD: < 75 mV
• VrefCA: <= 60 mV
• VrefDQ: <= 60 mV

Measure according to standard ripple measurement techniques.

Signal Integrity Measurements

Clock Measurements

Jitter-related parameters include period jitter, cycle-to-cycle jitter, and duty-cycle distortion. For example, at DDR4-2666:

Jitter can be measured manually or automatically. Manual measurement requires displaying about 200 clock cycles and adding measurements such as positive width, negative width, period, and frequency.

Automatic measurement requires the oscilloscope's DDR analysis feature (typically a licensed option). Select the clock test, the channel used for the clock, and the DDR rate. Run continuously to check for errors and export a report if needed.

Command and Address Measurements

Command/address signals to test include CS#, RAS#, CAS#, WE#, address lines and bank address lines. For DDR4 the setup and hold tests do not reference slope; the conditions are:

• tIS > tIS(base)
• tIH > tIH(base)

The reference voltage levels for setup/hold are AC 100% and DC 75% thresholds. It is useful to include CS as a reference in the test waveform since CA signals are valid when CS is low.

Write Data Measurements

Both read and write data measurements use DQS as the timing reference for DQ, not CLK. For DDR4 write measurements the focus is on eye diagrams rather than classic setup/hold windows used in DDR3.

Eye-width and eye-height requirements are shown below.

Example write waveform:

Test schematic:

tDQSS is the phase difference between CLK and DQS; example waveform:

Read Data Measurements

Key read parameters include tDQSQ, tQH and tDQSCK. Example measurement diagram:

tDQSQ requirements vary with DDR rate (values shown in vendor tables). tQH requirement: min = 0.38 * tCK.

Oscilloscope capture examples (DPO71254) for tDQSQ and tQH:

When testing, accumulate multiple captures to observe the overall waveform trends.

tDQSCK measures the relationship between the read data clock and read DQS. Example capture:

Parameter limits depend on DDR rate; refer to vendor tables for specific min/max values.

When testing read and write data, select representative high-bit and low-bit DQ lines for measurement.

Typical Limits by Speed

Vendor Test Items

Different memory vendors have similar test item sets. Example comparisons for Samsung and SK Hynix are summarized; both vendors measure clock parameters, duty cycle, timing, DQ/DQS parameters and power ripple. Vendor-specific thresholds and which signals are measured may differ. Refer to vendor-specific test documents for full details.

Summary

For DDR4 testing, manual testing is often preferable because manual read/write separation provides clear accumulated waveforms. Exhaustive testing of every signal is not always necessary; representative sampling across types is usually sufficient.