If PCB board size is my constraint ....and I have designed my circuit ...
1. How to optimize the layout of design for smaller space? 2. How to run simulations if any to do intelligent SI test?
Does packages by Cadence, Mentor support this kind of optimisation of layout?
Bowen
2017/3/2 23:23:38
Remarkable.It help me a lot. Thank you.
Mario
2017/3/2 23:23:38
Perfect post that I need. Enjoy reading it.
Bernard REMOND
2017/3/2 23:23:38
Useful!
Andrew
2017/3/2 23:23:38
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