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The sensitivity of electronic equipment is higher and higher, which requires the anti-interference ability of equipment to become stronger and stronger, so the PCB design become more difficult and most PCB engineers regard improving the anti-jamming capability as one of the key concerns. This article will introduce some tips for reducing noise and electromagnetic interference in PCB designs.
Based on years of experiences, 24 tips have been summed up to reduce noise and electromagnetic interference.
(1) Prefer low-speed chip to high-speed; high-speed chip is used in key places.
(2) By string a resistance, reducing and controlling the rate of change when circuits go up and down.
(3) Provide relay with a certain form of damping.
(4) Use the lowest frequency clock that meets the system requirements.
(5) The clock generator is as close as possible to the device using the clock. The shell of quartz crystal oscillator should be grounded.
(6) Circle up clock with the ground wire and the clock wire is as short as possible.
(7) I/O drive circuit should leave the edge of the printing plate instantly. The signal goes into the printed circuit board and from the high noise zone should be added to filter, reducing the signal reflection by stringing termination resistor.
(8) MCD useless end should be high, or grounded, or defined as the output, and the end of power supply in integrated circuit need to be grounded, do not vacant.
(9) Do not make the input end of idle gate circuit vacant; positive input termination of idle op amp is grounded and negative input termination connects output.
(10) Try to use 45 fold lines instead of 90 fold lines in PCB to reduce the external launch and coupling from high-frequency signal.
(11) Printed circuit board is distinguished by the frequency and current switching characteristics, the noise components and non-noise ones should be far.
(12) single-sided and double-sided board are adopting single-point power supply and single-point grounding; power and ground wires is as thick as possible, using multi-layer board to reduce the power supply and capacitive inductance if you are not sensitive to money.
(13) Clock, bus and chip select should be away from I/O lines and connectors.
(14) Analog voltage input line, notice the voltage side stays away from the digital circuit signal lines, especially to the clock.
(15) To the A/D class devices, digital and analog parts would rather unite rather than cross.
(16) The interference of clock line which is perpendicular to the I/O line is smaller than this when the lines are paralleled and the clock component pin is far from I/O cable.
(17) Component and decoupling capacitor pins are as short as possible.
(18) The key line should to be as thick as possible with protection ground on both sides. High-speed line is short and straight.
(19) Noise-sensitive lines do not parallel to high-current, high-speed switching lines.
(20) Do not route below quartz crystal and noise-sensitive devices.
(21) Do not form a current loop around weak signal circuit and low frequency circuit.
(22) Do not form a loop for any signal, if unavoidable, make loop area as small as possible.
(23) Make a complementary capacitor for each integrated circuit. Each electrolytic capacitor edge should add a small high frequency bypass capacitor.
(24) Using tantalum or cool capacitors of a large capacity instead of electrolytic capacitors for the circuit charge and discharge. The housing needs to be grounded when using a tubular capacitor.
fabian
2017/3/1 16:36:36
Really appreciate your content.I hope you write again soon.