FPGA device density continues to grow at approximately 2x per node, which is driving the ability for FPGAs to incorporate more of the system design into the devices. This means that companies designing new FPGA-based products continue to drive higher integration and, subsequently, more complexity into their system designs. This has led companies designing complex FPGAs to move increasingly towards licensing IP cores for the majority of the building blocks of their designs, as opposed to building their own in-house custom versions.
FPGA designers typically use IP from multiple sources ranging from internal to FPGA device vendors. In order to efficiently leverage IP from multiple sources, designers require synthesis and debug tools that support the portability of IP across technologies, along with the ability to properly handle the various forms of IP. The Synplify synthesis tools automate much of the handling of design IP by directly supporting vendor IP catalogs like Altera's Megawizards and Xilinx's IP catalogue.
In addition to the automated and correct handling of IP, the debug of complex FPGA designs with multiple sources of IP is challenging to FPGA designers. When the design fails to operate as expected, the FPGA designer has to determine what is causing the issue, which is only made harder if the design is developed by multiple teams worldwide. Distributed FPGA design development is creating a need to isolate and fix errors quickly throughout the design cycle. While FPGA vendors provide on-chip logic debuggers, they have limited visibility and traceability back to the RTL design. In addition, each change in the watched nodes requires a new recompile causing more time delays.
True debugger integration with synthesis tools can help immensely in finding and quickly iterating through bugs. Synplify Premier is integrated with the Identify RTL debugger, which allows designers to take advantage of the technology views within the tools to quickly instrument the design. Also, in addition to quick and easy setup of samples and triggering, Identify provides automation for mapping the hardware results back into the RTL. An FPGA designer can use RTL control flow statements like IF, WHEN, and CASE using design signals or busses.
There are times when FPGA designers need to over-instrument their design, but do not have enough resources to build a signal buffer large enough to capture all signals. The Identify RTL Debugger solves this problem by providing sample groups that allow the user to selectively sample groups of signals. Each sample group is exclusively available from the output of the debugger through a multiplexed path and shared IICEs. This helps meet the objective of the designer during the system bring-up phase of debug when the designer has not yet isolated the problem area and requires some trial and error instrumentation. Debug is an iterative process since it is rarely known where the sources of bugs in hardware design are prior to running a design. A common use model is to over-instrument a design to ensure a correct window into the design is obtained. Identify can provide this over-instrumentation capability without increasing data storage requirements.
By using signals or buses, designers have the flexibility to establish simple transition-based sampling or very complex state machine-based triggering that can be coupled with inputs and transition states to track down the most complex of system bugs. This type of versatile, iterative, and incremental debug methodology allows FPGA designers to deliver debugged designs quickly and easily, thereby ensuring design integrity and robustness.