Via is one of the important components of a multi-layer PCB. The cost of drilling is usually 30% to 40% of the cost of PCB board.
Vias can be divided into two categories: one for electrical connection between layers and the other for mounting or positioning of the device.
In terms of process, vias can generally be classified into three types, namely, blind vias, buried vias, and through holes.
Blind vias: Blind vias are located on the top and bottom surfaces of the printed circuit board, with a certain depth for the connection of the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture).
Buried vias: Buried vias refer to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board.
Through holes: throug holes pass through the entire circuit board and can be used to implement internal interconnections or as mounting holes for components. Since the via is easier to implement in the process and lower in cost, most printed circuit boards use it instead of the other two vias.
A via is mainly composed of two parts, one is a drill hole in the middle, and the other is a pad area around the hole. The size of the two parts determines the size of the hole. Obviously, in high-speed, high-density PCB design, designers always want the smaller the via, the better, so that more wiring space can be left on the board. In addition, the smaller the via, its own parasitic capacitance. The smaller, the more suitable for high speed circuits.
The reduction in hole size also leads to an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by the process techniques such as drilling and plating: the smaller the hole, the hole is drilled. The longer it takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the hole, there is no guarantee that the hole wall will be uniformly plated with copper. For example, the thickness of a normal 6-layer PCB (through-hole depth) is about 50Mil, so PCB manufacturers can provide a minimum diameter of 8Mil.
The via hole itself has a parasitic capacitance to the ground. If the via hole diameter of the via hole on the ground layer is known to be D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is similar to: C=1.41εTD1/(D2-D1) The parasitic capacitance of the via will have a major effect on the circuit by prolonging the rise time of the signal and reducing the speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, we can approximate the via hole by the above formula. The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, and the amount of rise time caused by this part of capacitance is: T10-90=2.2C(Z0/2)=2.2 X0.517x (55/2) = 31.28ps. It can be seen from these values that although the effect of the rise and delay caused by the parasitic capacitance of a single via is not obvious, if the vias are used multiple times in the trace for interlayer switching, the designer must carefully consider it.
The parasitic inductance of the via, the parasitic capacitance of the via has parasitic inductance. In the design of the high-speed digital circuit, the parasitic inductance of the via is often more harmful than the parasitic capacitance. Its parasitic series inductance weakens the contribution of the bypass capacitor and reduces the filtering effectiveness of the entire power system. We can simply calculate the parasitic inductance of a via approximation using the following formula: L = 5.08h [ln(4h/d)+1] where L is the inductance of the via, h is the length of the via, and d is the center The diameter of the hole. It can be seen from the equation that the diameter of the via has less influence on the inductance, and the greatest influence on the inductance is the length of the via.
Still using the above example, the inductance of the via can be calculated as: L = 5.08 x 0.050 [ln (4x0.050 / 0.010) + 1] = 1.015nH. If the rise time of the signal is 1 ns, then the equivalent impedance is: XL = πL / T10 - 90 = 3.19 Ω. Such impedance can not be ignored in the presence of high-frequency current. It is important to note that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground plane, so that the parasitic inductance of the via will be multiplied.
During the design process, we can try to follow the below stanards:
1. Consider about the cost and signal quality, choose a reasonable size of the via size. For example, for 6-10 layer memory module PCB design, 10/20Mil (drill/pad) vias are better. For some high-density small-size boards, try 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller size vias. For vias for power or ground, consider using larger sizes to reduce impedance.
2. the two formulas discussed above can be concluded that the use of a thin PCB board is beneficial to reduce the two parasitic parameters of the via.
3. The signal traces on the PCB should not be changed as much as possible, that is, try not to use unnecessary vias.
4. The power and ground pins should be punched near the hole. The shorter the lead between the via and the pin, the better, because they will lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce the impedance.
5. Place some grounded vias near the vias of the signal-changing layer to provide the most recent loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB. Of course, you need to be flexible in design.