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I am looking for some design guidelines (length, width, spacing) for solder thieves which are placed behind trailing pins of wave soldered SOICs. I'd appreciate it if some one could direct me to the appropriate reference. Also, has any one performed any experiments to determine the optimal solder thief design? Thanks for the help.
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David Soares
2/28/2017 3:48:38 PM
Great thanks for your helpful info. Really useful.
Waelson Negreiros
2/28/2017 3:48:38 PM
Bookmarked.Really helpful.
servis.av
2/28/2017 3:48:38 PM
Nice content you’ve posted in here
Jorge Arizaga
2/28/2017 3:48:38 PM
Your post answered my questions. Thanks a lot.