In designing high-performance data acquisition systems, engineers will carefully select high-precision analog-to-digital converters (ADC) and other components needed to simulate front-end adjustment circuits. After several weeks of design, simulate and optimize the circuit schematic, in order to catch the construction period, the designer quickly put the board layout and wiring together. After a week, the first prototype circuit board was tested. Surprisingly, the board performance is not the same as expected.
Has this scene happened to you?
Optimal PCB placement and routing is critical to enable the ADC to achieve the desired performance. When designing a circuit that contains mixed-signal devices, you should always start with a good grounding arrangement and use the best component placement and signal alignment to divide the design into analog, digital, and power sections.
The reference trace is the most critical of ADC layout, because all conversions are a function of the reference voltage. In the traditional successive approximation register (SAR) ADC architecture, the reference trace is also the most sensitive because the reference pin has a dynamic load to the reference source.
Since the reference voltage is sampled several times during each conversion, a high current transient occurs on this terminal, where the ADC internal capacitor array is turned on and charged. The reference voltage must remain stable for each conversion cycle and stabilize to the desired N-bit resolution; otherwise a linear error and a loss code error will occur.
Figure 1 shows the current transients during the conversion phase on a typical 12-bit SAR ADC reference terminal.
Figure 1 Current transient on 12-bit SAR ADC reference pins
Due to these dynamic currents, a high quality bypass capacitor (CREF) is required to decouple the reference pins. This bypass capacitor is used as a charge memory to provide instantaneous charging during period of high frequency transient currents. The reference bypass capacitors should be placed as close as possible to the reference pins and connected together with shorter and low inductance connections.
Figure 2 shows an example of a circuit board layout for a 14-bit dual ADC ADS7851 with two independent internal voltage references.
Figure 2 Dual ADC layout with two independent internal voltage references
In this four-layer PCB circuit board example, the designer uses a rugged ground plane just below the component and divides the board into analog and digital parts to keep the sensitive input and reference signal away from noise. He bypasses the REFOUT-A and REFOUT-B reference outputs with 10μF, X7R, 0805-size ceramic capacitors (CREF-x) to achieve optimum performance and connect them to components with small 0.1Ω series resistors, to maintain the overall impedance at low frequencies and constant. He also uses a wide trace to reduce the inductance.
I highly recommend putting the CREF on the same layer as the ADC. It is also advisable to avoid placing the vias between the reference pins and bypass capacitors. Each reference ground pin of the ADS7851 has a separate ground connection, and each bypass capacitor has a low inductance connection to the ground trace.
If you are using an ADC that requires an external reference source, you should minimize the inductance in the reference signal trace - from the reference buffer to the bypass capacitor to the ADC reference input.
Figure 3 shows an example of the layout of the 18-bit SAR ADC ADS8881 using an external reference and buffer. By placing the capacitor within 0.1 inches of the pin and connecting it to a 20-mil trace and multiple 15-mil ground guides, the designer keeps the inductance between the reference capacitor and the REF pin at a level less than 2nH. I recommend using a single, 10uF, X7R, 0805 size ceramic capacitor with a rated voltage of at least 10V.
The trace length of the reference buffer circuit to the REF pin remains should be as short as possible to ensure fast and stable response.
The correct decoupling of the REF pin is important to gain optimal performance. In addition, maintaining a low inductance connection in the reference trace keeps the reference drive circuit stable during the conversion, achieving the desired effect.
Figure 3 ADC layout with external reference and buffer