We have an unusual problem here and I'm reaching for more input if anyone can help??? We are an OEM manufacturer of PCA's. After a history of consistent quality designs, we have one small memory SIMM that is causing major headaches for us and our PCB mfgr. (a 1st class and reputable board-house). The PCB is designed to 6/5 design rules and is delivered to us after complete electrical testing. In post-production testing, we are finding 20-50% board failures in two separate production runs. Sometimes the boards work for 10-20 hrs. before failure. The affected traces are always found to be broken/open at the "heel" of a SMT pad where the trace connects to the pad. The PCB mfgr. has a 1 mil solder mask clearance that exposes the trace where it fails. The boards go through the HASL process and have gold-plated fingers for the SIM socket. It was suggested that the gold plating process could be affecting us somehow...is this possible? This design doesn't have teardrops, but has prompted us to use teardrops on every design since...(maybe this will help??) Why are the traces only "breaking" at the SMT pads??? I'd appreciate any insight.