Board design is a critical and time consuming task, and any problems require the engineer to exhaustively go through the design, net by net, and component by component. Arguably, board design requires equal care as chip design.
Typical board design flow consists of the following stages:
The first three stages take maximum time because the schematic review is a manual activity. Imagine a SoC board with 1000 or more connections. Reviewing each and every connection manually is a tedious task. It is almost impossible to check each, and this leads to problems in the final board, like wrong connections, floating nodes, etc.
In schematic capture, we face the following kinds of problems:
-Underscore errors: APLLVDD vs. APLL_VDD
-Capitalization issues: VDDE vs. vdde
-Signal short issues
-…and many more
In order to avoid these mistakes, there should be a mechanism by which the schematic can be reviewed in seconds. This is made possible by schematic simulation, which is often missing in present board design flows. By schematic simulation, the final output is observed at the required node; hence, it automatically takes care of all connectivity issues.
This is explained here with the help of an example project. Consider a typical block diagram of a board:
In a complex board design, the number of connections can reach into the thousands, and a minute change can waste a lot of time to get reviewed.
Schematic simulation not only saves design time, but also increases the quality of boards and increases the efficiency of the overall flow.
A typical DUT has the following signals:
The DUT has various signals which come after some pre-conditioning. There are various blocks like voltage regulators, op-amps, etc. which are used for signal conditioning. Consider the example of a supply signal which comes via a regulator:
Figure 3 Schematic of the example board
To verify the connectivity and perform an overall check, schematic simulation is used. Schematic simulation consists of schematic creation, test bench creation, and simulation.
In test bench creation, stimuli is given to the necessary inputs, and outputs are observed at the signals of interest.
This can be done by attaching probes to the nodes to be observed. Hence, node voltages and waveforms will indicate whether the schematic is correct or not. All signal connections will be automatically checked.
Figure 4 The schematic test bench and simulated values at various nodes
Let’s see a subsection of the above diagram in which probed nodes and voltages are clearly visible:
Hence, with the help of simulations, we can directly view the results and confirm whether the board schematic is correct or not. Furthermore, design change investigations can also be done by tweaking the stimuli or component values. A lot of time is saved for everybody involved in board design and review, and the chance of design correctness increases.