Despite the recent push toward high level synthesis (HLS), hardware description languages (HDLs) remain king in field programmable gate array (FPGA) development.Specifically, two FPGA design languages have been used by most developers: VHDL and Verilog. Both of these “standard” HDLs emerged in the 1980s, initiallyintended only to describe and simulate the behavior of the circuit, not implement it.
However, if you can describe and simulate, it’s not long before you want to turn those descriptions into physical gates.
For the last 20 plus years most designs have been developed using one or the other of these languages, with some quite nasty and costly language wars fought. Otheroptions rather than the se two languages exist for programming your FPGA. Let’s take a look at what other tools we can use.
1: C / C++ / System C
7: LabVIEW FPGA
9: VHDL / VERILOG
10: SPINAL HDL
1: C / C++ / System C
The C, C++ or System C option allows us to leverage the capabilities of the largest devices while still achieving a semblance of a realistic development schedule...although that may just be my engineering management side coming out.
The ability to use C-based languages for FPGA design is brought about by HLS (high level synthesis), which has been on the verge of a breakthrough now for manyyears with tools like Handle-C and so on. Recently it has become a reality with both major vendors, Altera and Xilinx offering HLS within their toolsets Spectra-Q andVivado HLx respectively.
A number of other C-based implementations are available, such as OpenCL which is designed for software engineers who want to achieve performance boosts byusing a FPGA without a deep understanding of FPGA design. Whereas HLS is still very much in the area of FPGA engineers who want to increase productivity.As with HDL, HLS has limitations when using C-based approaches, just like with traditional HDL you have to work with a subset of the language. For instance, it isdifficult to synthesize and implement system calls, and we have to make sure everything is bounded and of a fixed size.
What is nice about HLS, however, is the ability to develop your algorithms in floating point and let the HLS tool address the floating- to fixed-point conversion.As with many things, we are still at the start of the journey: I am sure over the coming years, we will see HLS increasingly used in different languages, making HLSsimilar to very low level of a software engineer’s C.
Python is an incredibly popular language used across several industries, taught in schools and universities and even used in embedded systems via micro python.
MyHDL is a python package that enables us to use python to design our FPGA; what’s more, it is open source and freely available. It is not however an HLS tool, so thedeveloper still needs to understand FPGA design techniques.Most algorithms implemented in FPGA start out at a high level using floating point numbers. MyHDL allows you to use the same language for the algorithmdevelopment as for your implementation. Languages that describe hardware implementations need to be able to describe concurrent operations. To achieveconcurrency, MyHDL uses generators, and communication between concurrent modules uses an object called a signal, which is within the MyHDL package.
MyHDL is interesting because it provides for a potentially powerful simulation environment by leveraging the power of the wider python language to generate testbenches and stimulus. This includes native support for databases, GUI’s and so on. MyHDL is supplied with its own simulation tool.The output from MyHDL comes in either Verilog or VHDL, which if you are providing IP to third parties can be very advantageous as you can easily match theirpreferred HDL, presuming they are using one. To implement your MyHDL design, and analyse the timing, you will need to generate the VHDL or Verilog output andpush it through the same implementation flow as you would for traditional FPGA design, in that sense it introduces an additional step in the process.
Of course MyHDL does have some limitations. Despite using python, it is not a high level synthesis tool: As such, the resultant code is still at a relatively low level,and we have to still push it through the standard implementation flow. With all that in mind, MyHDL is still an interesting language and has been used for both FPGAand ASIC implementations.
CHISEL, an acronym like VHDL, it actually stands for Constructing Hardware In a Scala Embedded language. It is another open-source language and was developed atUC Berkeley, the same university that gave us SPICE.
SCALA, the language around which CHISEL is based, was developed originally by a French university to compile down to byte code and be executed on the Java VirtualMachine (JVM). Within the FPGA world, we use CHISEL very similarly to MyHDL although there are some subtle differences: The first being that CHISEL is objectorientated, the second is in how we verify and use our CHISEL design.
CHISEL has two output formats, but unlike MyHDL, they are not Verilog and VHDL. Instead, CHISEL outputs a Verilog for hardware implementation and C++, with the C++ being used for verification with a software model. This presents a very interesting capability for large designs in that we can reduce the verification timesignificantly. CHISEL is currently being used on the OpenSOC project.
Just another (JAVA) Hardware Description Language is also another academically generated language, stemming from Brigham Young University. Again this is opensource and object orientated. This language, unlike the other languages presented, was last updated in 2006. I have included it, however, as it demonstrates theefforts that going on for a number of years to generate a traditional RTL replacement using a more common software language.
Differing from MyHDL and CHISEL, the output from JHDL is an EDIF netlist, this traditionally generated post synthesis. JHDL also comes with its own circuitvisualization tool, which enables you to see the circuit generated from your JHDL description, and a JHDL simulator. Although development of JHDL appears to havestopped, it has led to the development of RapidSmith, which was just announced by the same university group on the 12th May 2016.
BSV (Bluespec SystemVerilog) is a language developed by Bluespec Inc and is based around Haskell. This language is designed to be used with the Bluespec compiler(BSC), which is an HLS compiler. The BSC generates either synthesizable Verilog or executable System C. The simulation environment, called BlueSim, enables theengineer to simulate either the source BSV or the executable System C resulting from the compiler. In many ways, BSV is like CHISEL, although BSV is not open source.
It also presents a more well-rounded and easy-to-use ecosystem, as you would expect with a commercial product.
The objective of BSV is to close the gap between modelling and the actual RTL. The System C executables generated are cycle accurate with the Verilog allowing formuch faster simulation time. BSV is part of the wider Bluespec development environment.
This is one language that every FPGA engineer should be familiar with from university and the field of work. We use MATLAB to generate filters for signal processing, develop image processing algorithms and almost any other algorithm. It is however possible to go from MATLAB model to FPGA using the HDL coder. What makes it even more impressive is traceability is maintained as such that high integrity applications can be developed using this approach. I know of at least one DO-254 programme that developed its FPGA using MATLAB.
Like many of the languages mentioned here, HDL coder outputs either synthesizable VHDL or Verilog that you can implement within your FPGA development flow.
It has been a few years since I have used MATLAB (actually Simulink as that is also supported by HDL Generator). MATLAB enables the engineer to focus on algorithms at the high level, and, like many HLS approaches, allows us to increase the level of abstraction.
HDL coder enables you also to perform hardware (FPGA) in the loop testing and co-simulation to see the difference between the original algorithm and the implemented hardware algorithm, which helps you explore the design space.
7: LabVIEW FPGA
Now for something completely different. The LabVIEW frame work gives you a totally different way of programming your FPGA. For those unfamiliar with LabVIEW, it is a graphical language (actually called “G”). The catch with developing FPGAs using LabVIEW FPGA: You need to develop using specific hardware from National Instruments called Reconfigurable IO (RIO for short) modules. These modules are based around Xilinx FPGAs with the latest one being the Zynq. What is really cool with LabVIEW FPGA is the FPGA compilation uses a cloud-based option, which speeds up the compilation time significantly.
Because this language can generate FPGA bit files that are used within the ecosystem from a high-level design, this approach classifies it, in my opinion, as an HLS tool. We can then use the FPGA design within the LabVIEW environment or using a C based software environment which uses the NI Real Time system.
While NI FPGA development flow is rather different than traditional approach, it does allow the engineer to get the benefits of FPGA development without the need to be an expert. LabVIEW FPGA has been used to test CCD and CMOS Imaging devices which have gone on to take some extraordinary images of the universe.
A logical extension of the Verilog language combined with OpenVera and SuperLog languages, SystemVerilog has led to what has been called the first hardware design and verification language. That is, we can use SystemVerilog for developing the RTL for the FPGA, or we can use it for verification—an arena where it is very powerful.
While it builds upon the traditional Verilog language, the implementation side introduces several new features relating to procedural blocks, interfaces, and new data types. The verification side introduces new string handling data types, support for constrained random testing, design coverage, and assertions, which provides its power for verification.
SystemVerilog greatly differs from Verilog, however, in that SystemVerilog supports an object-orientated programming.
SystemVerilog has seen wide adoption within the verification arena due to its support of constrained random, coverage and assertions. These are becoming very important with increases in design complexity, as traditional HDL languages do not support these natively, although open-source packages are available that do. When it comes to implementation, the adoption has been a little slower. Still, SystemVerilog a language to watch out for.
9: VHDL / VERILOG
As I mentioned in my introduction, VHDL and VERILOG are the current staples of FPGA design, both having been developed in the 1980s. VHDL stems from the US Department of Defense and Verilog from the commercial sector.
Both languages provide structures to describe the inherently parallel nature of FPGA / ASIC development. Due to their initial use to describe the behavior of the circuits prior to the generation of synthesis tools, these languages also support test benches to test the design being implemented.
Over the years, both languages have had a number of updates to improve the implementation and verification aspects. At times, the languages were updated for a long time before the industry toolset supported it fully. Often, it is up to the end user to request implementation of certain features of the language.
With the increases in device size and complexity over the last few years, the days of these traditional HDLs may be declining. However, I cannot see them being fully replaced in the immediate short term as sometimes we need that hand bit of crafted VHDL/Verilog to get the final performance boost.
We must also consider that a number of languages and tools presented here also output to either VHDL or Verilog, so I cannot see them disappearing in the short term. Their use, however, as a design entry language will reduce.
10: SPINAL HDL
This is the latest HDL I discovered, only coming across it when it was released at the end of May 2016. Again this language, like many of the ones presented here, outputs a VHDL file that is used in your simulation and synthesis tools. It does come with a development IDE, but seems to be missing a simulation environment, hence the recommendation to use your normal HDL tool chain.
SPINAL appears to be a higher level language that enables you to create complex structures simply. It appears to be very similar to CHISEL being both object orientated and based upon SCALA. However, SPINAL is supposed to address some of the issues regarding multiple clock domains and includes support using existing VHDL and Verilog IP.
As a fairly new language, SPINAL may take a while before it becomes established.