Decoupling caps and PCB layout
When it comes to the finer details of pcb layout.
Here is a example of a recent board of mine, and I have highlighted three of the decoupling caps.
The MCU is a LQFP100 package and the caps are 100nF in 0402
packages. The vias connect to ground and power plane.
The top cap (C19) is placed according to best practices. The other two are not. I have not found any problems. But the board has never been outside the lab.
My question is: How big a deal is this? As long as the tracks are short, does it matter?
You should have the vias close to the capacitor pads, to minimise inductance. The capacitor should be close to the supply and ground leads of the chip. The routing in the second image should be avoided, and the first isn't ideal. If that is a prototype, I'd modify the decoupling for the production version.
Proper bypassing, grounding, visualizing and dealing with the high frequency loop currents really matters. In this case it contributed to make the product better and cheaper at the same time.
The decoupling caps have two duties. One is as a power reservoir, the other is for noise filtering. The cap looks like a low-pass filter to the input. Only the filtering would be affected by the routing.