You should have the vias close to the capacitor pads, to minimise inductance. The capacitor should be close to the supply and ground leads of the chip. The routing in the second image should be avoided, and the first isn't ideal. If that is a prototype, I'd modify the decoupling for the production version.

Proper bypassing, grounding, visualizing and dealing with the high frequency loop currents really matters. In this case it contributed to make the product better and cheaper at the same time.

The decoupling caps have two duties. One is as a power reservoir, the other is for noise filtering. The cap looks like a low-pass filter to the input. Only the filtering would be affected by the routing.