ALLPCB
Overview
This article describes the similarities and differences between pre-simulation and post-simulation in IC design. A complete circuit design typically includes both pre-simulation and post-simulation, which are key parts of chip verification. In complex chip designs, verification can consume 60%–70% of the overall design flow time. The objective is to verify chip functionality thoroughly as early as possible, so issues can be exposed and resolved to ensure correct operation.
Commonalities
Both pre-simulation and post-simulation fall under the scope of digital verification and involve building a verification environment, which can be time-consuming. In practice, the tools used for both phases are largely the same.
Problems Addressed
Pre-simulation (also called functional simulation, behavioral simulation, or RTL simulation) verifies whether the circuit behavior under idealized conditions matches the design intent and specification. Post-simulation (also called timing simulation, dynamic timing simulation, or post-layout simulation) targets the post-layout netlist, incorporates timing analysis, and verifies functional correctness after layout and routing. In short, pre-simulation focuses on functional correctness, while post-simulation focuses on timing correctness.
Focus Differences
Pre-simulation mainly validates logical functionality and typically does not model gate delays or interconnect delays in detail; it lacks the actual timing information of internal logic cells and wiring. Post-simulation, in addition to device parameters, must consider parasitic effects of interconnects, which is why parasitic extraction is required in the backend. Interconnect resistance, mutual inductance between nearby wires, and coupling capacitance to substrate and adjacent lines can introduce noise, crosstalk, and reflections. These effects create signal integrity issues and voltage fluctuations that may lead to signal distortion or functional errors. Extracting parasitic parameters and reanalyzing them to assess signal integrity is therefore important.
Placement in the Flow
A clear distinction is the placement of layout and routing in the flow. Pre-simulation is performed at the RTL design stage, while post-simulation is performed after placement and routing. After place-and-route, the shapes, sizes, and relative positions of transistors and other devices are fixed, which effectively defines the manufactured chip structure. Different layout choices produce different parasitics. For example, the distributed capacitance between metal interconnects and the substrate depends on the layout; line length and routing paths affect parasitic capacitance and resistance. Other parasitic effects are similarly layout-dependent.
Simulation Results
Pre-simulation is generally faster and focuses on logical functionality. Post-simulation, with extracted parasitic parameters included, better reflects actual chip behavior and is closer to the real operating conditions, but it requires more runtime. Discrepancies between pre- and post-simulation results can occur and are often due to their differing emphases on logic versus timing and parasitics.
