Verilog Design Guidelines Overview

Introduction

Verilog guidelines are essential for good IC design. This article covers coding practices, module instantiation, operators, and module design templates. Goal: use the simplest and clearest approach to produce readable and efficient code.

1. Coding Practices

Unused syntax should be avoided.
Use a limited set of syntactic styles; the main styles are described below.
Circuit design structure can be organized in several common ways; choose the one that best fits the design.
Key points for circuit design are listed below.

[1] One always block should drive only one signal.

Do not write always blocks that drive multiple independent signals. Instead, structure code so each always block describes how a single signal is produced; this simplifies debugging, analysis, and maintenance.

[2] A signal should be driven by only one always block.

Avoid designs where the same signal is assigned in multiple always blocks.

[3] An always block should describe the conditions under which a signal takes specific values. All relevant conditions should be considered.

[4] Conditionals should use only if-else and case statements. Do not use other forms, including casex.

[5] Always blocks that include posedge or negedge describe D flip-flops and are sequential logic.

[6] Use combinational logic when an immediate result is required; use sequential logic when a one-cycle delay is acceptable or required.

2. Module Instantiation

Understand instantiation from simple to complex cases.
Use consistent instantiation styles.
Parameterized instantiation: use parameters to configure modules where appropriate. See parameter usage.