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This article discusses the Global Set/Reset (GSR) signal and its impact during Vivado simulations.
When designing for Xilinx FPGAs in Vivado and running a simulation, you will notice a signal named GSR in the waveform viewer. This signal typically starts high (logic 1) and transitions to low (logic 0) around the 100 ns mark.
The GSR signal originates from a file named "glbl" , which Vivado automatically includes during simulation startup. It represents a global reset signal within the FPGA fabric used to force all registers into a known initial state.
In many behavioral simulations, the GSR signal has no noticeable effect and is often ignored. However, it plays a crucial role in post-synthesis timing simulations.
Impact on Timing Simulation
A bug observed during a timing simulation highlights its importance. Consider a scenario involving an AND gate whose inputs are driven by the outputs of asynchronously reset registers. During the period when GSR is high, even if both register outputs are high, the AND gate's output may incorrectly remain low. Once GSR de-asserts (goes low), the gate's output behaves as expected.
This behavior is because post-synthesis timing simulations do not use the original Verilog source code. Instead, they use a netlist composed of primitive components from the FPGA's simulation libraries.
By examining the library files (specifically, the UNISIMS library), it can be found that primitives like the FDCE (D-type flip-flop with Clock Enable and asynchronous Clear) are sensitive to the GSR signal. While GSR is asserted high, the outputs of these primitives are held in their initial state and will not change in response to their data inputs.
Recommendations
To avoid simulation mismatches, ensure that the design's own reset sequence and valid signal activity begin only after the GSR pulse has completed. It is recommended to start applying valid signals or de-assert the user-defined reset after the 100 ns mark when GSR typically goes low.
In Vivado simulations, the GSR signal is fundamental to understanding design initialization. The simulator activates GSR at time t=0 to mimic the hardware's state immediately after FPGA configuration, forcing all controlled registers to their initial values. After GSR is released, the user-designed logic, including any custom reset signals, begins to operate normally. Observing the timing of glbl.GSR is a key step in verifying that the design's startup and reset behavior function as intended.
