ALLPCB
Overview
These are all aspects of the same issue. When writing RTL code, you must be clear about the goal: a physical implementation.
The core difficulty in code quality and design is making the design easy to implement while ensuring the implemented result matches expectations. It is not about how "pretty" the code looks.
Clean code does make maintenance and debugging easier, but that is a secondary benefit.
Key Technical Challenges
The main challenges are performance, power, area, and timing optimization.
Generally, pure coding is not extremely difficult. With detailed design documentation and solid coding experience, implementing the RTL is usually manageable.
Different Design Styles
In the IC community there is a saying that highlights individual preferences: designers have different habits. Some prefer grouping multiple variables in the same always block to reduce code size, while others prefer very explicit code for better readability. Different thinking modes lead to different ways to handle asynchronous logic: some use FIFOs, others use handshakes; some implement using combinational logic, others use sequential logic. For example, a sequence detector can be implemented with a state machine or with a shift register. These coding choices can lead to very different synthesis results.
Example: AXI Master
Using an AXI master design as an example, the implementation difficulty is not huge. Key points include: FIFO handling for data and control, controlling outstanding depth, managing channels, and implementing back-to-back transfers with combinational logic where appropriate.
If the AXI master is implemented simply, it is not hard. The first difficulty is how to support back-to-back transfers and achieve maximum throughput. One approach is to add combinational logic between consecutive transfers to avoid unnecessary cycles.
Timing and Pipelining
However, adding combinational logic can create timing issues because the added delay may be too large for the target clock frequency. The standard mitigation is pipelining: break up the combinational logic along the critical path by inserting registers. This itself requires careful work: it may not be enough to add a register on a single path, and registers may be needed on all paths that converge before a register. For example, when registering an AXI interface you cannot only register the address channel; other channels often need registration as well to satisfy protocol timing and handshake requirements. In practice, tools such as SpyGlass and PrimeTime (PT) reports are used to analyze the design and address issues one by one.
Area vs. Outstanding Depth
Area is another frequent concern. For AXI master performance, a larger outstanding capability is usually better, but wide buffers increase area and are typically implemented with SRAM, which grows cost. One textbook solution is time-division multiplexing, but that is not always applicable because channels are independent. In practice, outstanding depth is often parameterized based on the application scenario, for example considering the capability and requirements of the upstream IP. Time-division multiplexing is more suitable when computational units or memory can be reused, which requires a clear understanding of the software use case and algorithms.
Power Optimization
Power optimization covers both static and dynamic power at the cell level and clocking or frequency choices. At a higher level, power domain optimization is critical: decide which logic must be powered on together and which can be powered down. For example, a bridge and TX/RX logic can be shut down when no transmission is expected, while certain power management logic and configuration registers may need to remain always-on.
Final Advice
When implementing RTL, keep these considerations in mind. Do not focus solely on functional implementation; if the backend cannot close timing or performance targets are not met, you will go through repeated modifications that increase the risk of introducing bugs and significantly slow the project.
