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Leading chipmakers worldwide are racing to deploy a new generation of transistors based on gate-all-around (GAA) architectures. Although companies are at different stages of transition, they intend to integrate these "nanosheet" transistors at 3 nm and 2 nm nodes, with potential high-volume production starting in 2024 and 2025.
Companies such as Intel and TSMC will need time to realize the full potential of these transistors, and the broader semiconductor industry will take time to feel the full impact of the transition. Ultimately, these improvements are expected to become the standard for CPUs, GPUs, and other advanced logic chips used across domains from artificial intelligence to high-performance computing. The new devices promise faster switching and lower power, addressing limitations of FinFETs that have dominated the industry.
Nanosheet transistors will not rescue Moore's Law nor solve all challenges faced by foundries at the most advanced nodes. To address those challenges, fabs are pursuing various innovations, such as backside power delivery (BSPD), to extract more performance from interconnects while saving power.
They are also adopting new design methodologies, notably system-technology co-optimization (STCO), which involves connecting small chips with 2.5D and 3D advanced packaging.
Although nanosheets have limits, the industry is pushing the transition. Intel plans to introduce RibbonFET starting at its "20A" node, which the company has indicated will be enabled in the first half of 2024. TSMC plans to adopt nanosheets at its 2 nm node in early 2025. Samsung, a smaller player in logic markets, introduced a variant called MBCFET and deployed a 3 nm node in 2022.
To better understand the rationale and unique advantages behind nanosheets, Julien Ryckaert, vice president of logic technology at imec, shared his perspective.
Why did the industry move from planar transistors to FinFET?
Nanosheet transistors are effectively an evolution of FinFETs. The main driver for moving to these 3D structures was short-channel control.
As gate length is reduced in planar transistors, it becomes increasingly difficult to maintain isolation between source and drain and to ensure sufficient off-state voltage when the transistor is turned off. This phenomenon is known as the short-channel effect, and the ability to mitigate it is commonly quantified by the subthreshold slope.
As gate length shrinks, the drain gets physically closer to the source, making it harder to preserve isolation. Designers therefore look for ways to confine the channel so that when the transistor is off, the field within the semiconductor is strong enough to keep source and drain isolated.
The focus moved to fin devices: protruding silicon fins etched from the wafer, which the gate wraps around to ensure good off-state control and maintain acceptable subthreshold slope as devices scale.
Were there other forces driving FinFET adoption?
Ryckaert noted that much of the channel width (W), which correlates with the current needed to switch a transistor, is in the vertical direction—the height of the fin. Taller fins create more W and therefore higher drive current.
This was advantageous for FinFET scaling because it enabled very compact transistors with sufficient drive current. Foundries exploited this by reducing the number of fins per transistor and compensating by increasing fin height. If you want to shrink W in a planar transistor, it must occupy more lateral space.
Consequently, standard cells evolved from three-fin devices to two-fin devices. The scaling "knob" used in FinFET eras was fin-height scaling: you could scale standard-cell layouts without scaling track pitch by reducing the number of fins while increasing fin height. So two supporting arguments for FinFET adoption were improved electrostatic control and improved efficiency.
Why replace FinFET?
Ryckaert argues that while the move from planar to fin devices was logical, nanosheets will be needed because at extreme scaling FinFETs struggle to deliver the same benefits.
The push to nanosheets is primarily about electrostatics. With fins fixed to the wafer, you require very straight, tall silicon fins from top to bottom to ensure precise channel control. However, fin profiles are never perfectly straight, and some leakage from the fin base is inevitable. Some major foundries are attempting to improve fin profiles to secure electrostatic control.
At the same time, everyone wants to reduce gate length. But increasing fin height and gate length together while maintaining the same electrostatic control becomes increasingly challenging.
The industry is therefore moving to full GAA structures, where the channel is wrapped on all four sides to achieve a stronger gate field, enabling robust on/off behavior and reduced leakage. This allows further gate-length scaling within the nanosheet device.
Is FinFET scaling no longer sustainable at leading nodes?
As transistors shrink, eventually each device ends up with just a pair of fins. The next step is to consider single-fin devices, but a single-fin must be twice as tall to match the drive current of a dual-fin device. For example, a dual-fin scenario might use 50 nm fins; a single fin would need to be 100 nm tall, which is very tall and hard to manufacture cost-effectively.
Moreover, parasitic effects that accumulate in such tall structures—most notably capacitance and resistance—erase the advantages of a more compact layout. So a 100 nm single fin is not equivalent in performance to two adjacent 50 nm fins.
That explains why firms are investing in a transition to nanosheets and why different foundries follow different development paths. Some fabs introduced nanosheets earlier because at these dimensions FinFET and nanosheet designs compete to balance device efficiency, drive, and parasitics.
There is a limit to how close two fins can be, determined by how much metal you can pack between them to form the gate. At some point, you run out of room for another fin pair. Without nanosheets, you cannot achieve the same power and performance gains.
If a leading foundry has mastered fin fabrication, it will try to extract maximum value from FinFETs. The decision depends on manufacturing capability, perceived advantage, and how quickly a company wants to go to market. Some companies are trying to seize the nanosheet opportunity quickly.
In power and performance terms, nanosheets can be roughly comparable to FinFETs today. But eventually a move to nanosheets is inevitable because FinFETs become unscalable and no longer provide more transistors per unit area.
For that reason, the industry long ago stopped naming process nodes after any specific transistor measurement and instead uses node names as indicators of process advancement.
Do companies actually use nanosheets to reduce transistor footprint? Compared with FinFETs, nanosheets appear more focused on improving transistor performance rather than reducing area. Area savings seem secondary for nanosheets.
Another perspective is that scaling forces you to reduce standard-cell area for both nFETs and pFETs used in CMOS logic. You analyze layout limits: how far can fins be separated, how much spacing is required for correct operation, and so on. At some point you realize you can no longer place two fins in the same device space; you can only put an nFET on one fin and a pFET on another.
Planar nanosheet devices allow better use of available area to create larger effective channel width compared with FinFETs and to pack transistors together to increase drive capability.
When comparing power, performance, and area of FinFETs versus nanosheets at equivalent dimensions, FinFET performance begins to degrade around the 2 nm node. Nanosheets can continue to deliver the performance, power, and area improvements companies want today, but the gains are incremental rather than sudden.
What else is needed to bring nanosheet-based chips to market?
Ryckaert says that integrating a broad range of devices for I/O and standard CMOS platforms will be very challenging. Co-integrating other device types with nanosheets presents many difficulties. That implies a need to design a large amount of new IP to ensure SoC subsystems function correctly; otherwise I/O may be unavailable.
Although not directly caused by nanosheets, the transition coincides with many other changes in how semiconductor companies design. One additional shift planned at the 2 nm node is backside power delivery.
For both foundries and fabless companies, many changes are happening in parallel.
Are there unique advantages of nanosheets beyond density?
Ryckaert points out that while FinFETs have discrete fin counts—four fins, three fins, or two fins—nanosheets allow modulation of sheet width in a near-continuous way.
Manufacturing this precisely is challenging, but the ability to tune sheet width from, say, 25 nm to 20 nm, 15 nm, or 10 nm offers another optimization knob for SoC power and performance because channel width adjustments affect parasitic capacitance. If foundries can master this, fabless companies will gain finer power-performance trade-offs.
Only minor process changes are needed to tune this, which explains why it takes time to become broadly available. As FinFET options are exhausted, the industry is shifting focus to other innovations, particularly chiplets and advanced packaging.
Will nanosheet transistors have the same broad impact as FinFETs?
Ryckaert believes nanosheets are another tool in an expanding toolbox; the era when transistors alone dominated the entire semiconductor roadmap is over.
Maintaining density scaling with new devices is important, and achieving tighter transistors will remain a key element of scaling.
However, device area and performance are not determined solely by channel and transistor attributes; they also depend on how you access devices. The three major foundries have markedly different middle-of-line strategies, indicating room for innovation and new solutions.
In the future, 3D chip stacking and chiplet approaches may become increasingly important to supplement the transistor roadmap. A key issue with nanosheet transitions is SRAM: scaling SRAM density compared with FinFETs is difficult or limited. Because a processor can contain a large fraction of SRAM, an inability to scale SRAM would mean a significant portion of a product does not scale. That forces chip designers to seek alternative solutions to address the bottleneck.
