ALLPCB
01. Gain behavior near amplifier Psat
Q: Hi, I simulated a single-stage differential CMOS power amplifier and found Psat around 15.2 dBm, but the input power is already about 15 dBm so there is almost no gain left. I have seen single-stage PAs that still have some power gain at Psat, so what might be the issue?
A: The small-signal gain is quite low, only about 8 dB.
Q: Yes.
My operating frequency is around 28 GHz. The transistor total width is 320 μm, biased in AB class, common-source configuration. Is the small single-stage gain the reason? I see most designs use two or more stages, but I'm currently learning and only designed one stage.
A: The amplifier is compressing a lot. To get higher output power you need other approaches.
Q: If I want a single-stage PA to still have power gain at Psat, do I need a higher small-signal gain, e.g., by increasing DC bias? Or would designing a two-stage PA avoid this issue?
A: Higher small-signal voltage gain alone does not directly increase output power. Power depends on both voltage and current; paralleling devices increases current and thus output power. Two stages increase gain but do not change saturated output power much.
Q: Normally should there be some power gain at saturation? Is it abnormal that the power gain is nearly zero as in my plot?
A: The curve looks fine. Check the 1 dB compression point; if compression is severe the gain can go to zero.
Q: I checked: the 1 dB compression point is low, around 7.4 dBm, much lower than Psat. So the compression is severe and the linearity is poor.
A: 1 dB compression means the linear gain drops by 1 dB. I see some output around 13 dBm in your curve; use finer power steps.
Q: Thanks. I only know how to compute current density per finger. How is power density calculated?
A: See if the PDK provides that information.
Q: Thanks.
02. Improving convergence in GaN PA simulations
Q: When simulating GaN PAs I often get convergence problems, discontinuous model data, or no results. What methods improve convergence? Any references or experience would be helpful.
A: Change the HB solver type or harmonic order.
Q: I can reduce the order to two. Which solver type should I use?
A: Don’t sweep with HB. Use SWEEP PLAN and try the Krylov solver.
Q: I will try that, thanks.
A: Note that lowering harmonic order may reduce accuracy.
A: There are online posts specifically about HB convergence that may help.
Q: Example reference: https://zhuanlan.zhihu.com/p/57022677
A: The ADS help also has sections on nonconvergence; check those.
Q: Which help topic specifically? Can you point to it?
A: The default HB solver is automatic; switch to Krylov.
Q: Thanks, I found it and will try.
A: Sometimes small tuning of matching components also helps convergence.
03. Why small-signal gain differs when HB is on or off
Q: Have you seen different small-signal results with HB on versus HB off? The gain drops by about 2 dB and the feedback is slightly different.
A: Are the DC operating points different?
Q: Yes, they differ.
A: If you run HB and then open HB components, the operating point changes. For RF simulations the tool finds the most nonlinear operating point (typically at the target frequency); small-signal calculations are linearizations around that solution. If you don't run HB you are not evaluating the RF operating point, so the results will not match.
04. Handling TRAN simulation errors
Q: When running a transient simulation in ADS I get this error. How to handle it?
A: I usually adjust two time parameters; sometimes they need to match. I’m not fully sure why it happens, but tweaking timings or the circuit often resolves it.
05. Does the E8257D signal source include a DC blocking capacitor?
Q: Does the E8257D signal source have an internal DC blocking capacitor? I'm testing a die without on-chip DC blocking and wonder whether feeding RF from the source will affect device bias.
A: Check the instrument help. If not testing on-wafer you can add an external blocking capacitor.
A: You can also check with a multimeter in resistance mode to verify.
06. What is tuned during PA bench tuning?
Q: What do people adjust when tuning a power amplifier?
A: Many things: bias, output matching, etc. Simulation models used in the Chinese market may not be as accurate as some foreign vendor models (for example, Skyworks or Qorvo), where manufacturers provide their own calibrated models.
Q: Is output matching about impedance tuning?
A: Load-pull is used to tune for requirements such as power or linearity.
07. Inter-stage matching in LNA design
Q: For inter-stage matching in an LNA, how should the output impedance of the first stage and the input impedance of the second stage be chosen? How to balance gain, VSWR, and noise? Should both be matched to 50 ohm and then connected, or should the stage impedances be conjugate-matched directly?
A: Prioritize the noise figure of the first stage; the second stage has less impact. Inter-stage matching does not have to be 50 ohm; conjugate matching between stages is fine.
Q: If both are matched for maximum gain, will VSWR be poor?
A: Essentially the transformations are equivalent if viewed as passive networks. If matching on-chip, conjugate matching usually yields maximum small-signal gain and acceptable VSWR.
Q: Are there references on this? Papers often only briefly mention it.
A: Check vendor and textbook documentation. For LNAs, the first stage is the most critical for noise; later stages focus on gain and output P1dB. MMIC inter-stage matching is often used to flatten gain; otherwise conjugate matching suffices. On-chip, if the stages are not 50 ohm, all passive elements need adjusted and test probing becomes harder since probes are calibrated to 50 ohm. In general, make the first stage optimized for noise and ensure the first input and last output are 50 ohm; intermediate stages can be designed for loss versus complexity trade-offs.
Q: How should the LNA output be matched to a mixer input?
A: Use large-signal or HB/SP simulations of the mixer input impedance under operating conditions, then design a matching network to conjugate-match across the desired bandwidth and make minor adjustments for bandwidth.
08. Impedance calculation for RLC resonant circuits
Q: Can someone help with this example problem from the textbook "RF Microelectronics", 2nd edition?
A: Refer to phase-locked loop transfer functions and textbook derivations.
Q: Thanks.
A: Look at the first chapter of high-frequency circuit texts. The circuit is typically treated as a parallel RLC for filter designs; Q formulas follow from the linear term in the impedance expression. The frequency shown may be a suppression frequency and you may need to substitute detuning frequency in formulas.
09. Why Load-pull fails to converge at very high or low input power
Q: In load-pull, why does the simulation fail to converge when the input power is set too high or too low? Changing convergence radius and center can help, but what's the cause?
A: At low power the load-pull circle may move outside the impedance region of interest.
Q: Why does the circle move at low power?
A: The optimal load for Ropt is typically defined for saturation, not for small-signal. The loadline differs, so you should often look at ZL corresponding to P3dB or the relevant compression point.
10. Alternatives to long interconnects in MMICs
Q: The simulated circuit meets performance but the traces are long. Can the line length be effectively shortened? I tried narrowing the trace width and had little impact.
A: What do you mean by "equivalent"?
Q: I mean reduce the physical size of microstrip lines.
A: Adjust the matching at the transistor combination point, or add a series capacitor to shift the matching point, so microstrip runs can be shortened. If the frequency is not very high, you can use lumped capacitors and inductors to replace transmission-line sections, but at high frequency consider Q and parasitics.
A: For MMIC PA output matching, a 3000 μm microstrip may be normal if it meets requirements.
Q: My design is at 6.5 GHz; I calculated that 1000+ μm corresponds to about 50 degrees electrical length.
A: If bandwidth requirements are low, use lumped elements.
Q: Meaning use discrete-capacitor/inductor equivalents?
A: Yes, but high-frequency capacitors and inductors may be hard to find and their models are not ideal. Try it in simulation first.
A: What is your process dielectric constant?
Q: 13, gallium arsenide.
A: With lower dielectric constants you may get longer electrical lengths; design choices depend on process.
11. Does an inductor with specified Q include parasitic capacitance?
Q: Does an inductor specified with a Q value also include parasitic capacitance?
A: Q measures how well the inductor stores RF energy and is not directly the same as parasitic capacitance. The device is still an inductor and its inductance value may vary with frequency. To verify, run an S-parameter simulation and extract the inductance, or compare against an ideal inductor's S-parameters.
A: The current is in milliamps by default. For MOSFET, transconductance gm is dIDS/dVGS, so an AC sweep that perturbs VGS by 1 mV will show the corresponding change in IDS.
