I3C Interface Communication Basics

Overview

I3C is a serial communication protocol for embedded systems that provides much higher data throughput and additional features compared with I2C. I3C enables designers to improve system performance and add features such as hot-join, in-band interrupts (IBI), and high data-rate (HDR) modes. I3C is backward compatible and can interoperate with legacy I2C targets. A summary of differences between I3C and I2C appears in the original table.

Bus speed and signaling

A major change from I2C is clock speed. I2C commonly operates at 100 kHz, 400 kHz, or 1 MHz, while I3C can reach up to 12.5 MHz. One key reason for this higher speed is the use of push-pull drivers in I3C. The bus switches between open-drain and push-pull drivers depending on bus state. Open-drain is used during initial addressing or arbitration when multiple targets may try to drive the line, whereas push-pull is used during unidirectional communication when no other device will transmit at the same time.

Unlike I2C, I3C does not require external pull-up resistors because the active controller on the bus provides pull-up functionality. I2C supports a wide range of supply voltages, commonly 3.3 V and 5 V. I3C defines three nominal voltage levels: 1.2 V, 1.8 V, and 3.3 V, though other operating ranges are allowed.

Addressing and dynamic addresses

I2C supports 7-bit and 10-bit addressing. I3C uses only 7-bit addressing but adds dynamic addressing: the active controller assigns a dynamic address to each target to avoid address conflicts. Dynamic address assignment occurs during bus initialization.

In-band signaling and interrupts

Unlike I2C, which has no mechanism for a target to alert the controller without extra I/O lines, I3C targets can signal interrupts using the serial data (SDA) and serial clock (SCL) lines, making it a true two-wire protocol. The same in-band signaling is used to implement hot-join so that devices can join the bus after initial address assignment. In-band interrupts (IBI) and address arbitration are discussed in more detail below.

Active and secondary controllers

I2C supports multi-controller buses where multiple devices can act as controllers but only one is active at a time. In I3C, only one device may be the active controller; other capable devices may request to become the active controller and are called secondary controllers. When a secondary controller is not acting as the active controller, it behaves as an I3C target.

Compatibility with I2C targets

I3C supports communication with legacy I2C targets provided the I2C target:

uses a 7-bit address,
does not perform clock stretching, and
ideally includes a 50 ns input filter on its inputs.

If these conditions are met, the I2C target is compatible with an I3C bus. Some I3C devices can operate as I2C targets until they receive a dynamic address. In I2C mode, an I3C device uses a static address for communication; the static and dynamic addresses need not match but can be set identically if required.

Bus configuration and data transfer

Before any communication on an I3C bus, the bus must be configured and dynamic addresses assigned to targets. Communication then begins similarly to I2C: a START condition is generated, followed by the 7-bit dynamic address and the R/W bit, and then an ACK or NACK from the target. I3C uses 9-bit serial transfers like I2C, but the 9th bit has been repurposed from ACK/NACK to the transfer bit (T bit). The T bit has two roles: when the controller writes to a target, the T bit provides odd parity for the transmitted data byte; when the controller reads from a target, the T bit serves as a data-end flag. This flag may be asserted by the controller to indicate it has finished reading, or by the target to indicate no more data are available. The controller completes data transfer by generating a STOP or RESTART condition on the bus. Note that if RESTART is used, the header is transmitted push-pull because no arbitration is taking place.

An important change in I3C is the elimination of clock stretching. In I2C, clock stretching gives targets extra time to prepare returned data. In I3C, the clock is driven only by the active controller in single data-rate (SDR) mode, so clock stretching is only possible under limited controller-executed conditions. Targets can, however, indicate speed constraints during bus initialization to specify operating frequency, read/write turnaround time, and other timing parameters.

Common Command Codes (CCC)

Common Command Codes (CCC) are a new concept in I3C. The active controller uses CCCs to initialize and configure the I3C bus. CCCs can be broadcast to all targets or sent privately to a specific target. To send a CCC, the controller first addresses 7'h7E/W. All I3C devices must acknowledge and listen to this address; I2C devices cannot match it because 7'h7E is reserved under the I2C specification. The controller then sends the CCC code. For write-type CCCs, the controller continues sending data as required. For read-type CCCs, the controller sends any parameters, issues a RESTART, and then reads data.

Important CCCs include, but are not limited to:

Enter dynamic address assignment (ENTDAA)
Set new dynamic address (SETNEWDA)
Enable events (ENEC) / Disable events (DISEC)
Reset dynamic address assignment (RSTDAA)
Set/get read length (SETMRL / GETMRL)
Set/get write length (SETMWL / GETMWL)
Get device characteristics register (GETDCR)
Get bus characteristics register (GETBCR)
Target reset action (RSTACT)
Enter high data-rate mode (ENTHDRx)

There are also HDR Entry CCCs that indicate the active controller is entering one of four HDR modes (0, 1, 2, or 3).

High Data-Rate (HDR) modes

The I3C specification defines four HDR modes:

HDR double data rate (HDR-DDR) [mode 0]
HDR ternary symbol pure bus (HDR-TSP) [mode 1]
HDR ternary symbol legacy bus (HDR-TSL) [mode 2]
HDR bulk transport (HDR-BT) [mode 3]

HDR changes data encoding rather than clock rate. Basic I3C communication does not require HDR. Devices that do not support HDR will ignore HDR communication until they detect exit from HDR mode.

In-band interrupts (IBI) and arbitration

Unlike I2C, targets in I3C can generate a START condition when the bus is idle to issue an IBI. When the active controller detects a START from a target, it supplies the clock to complete the transaction. If two targets attempt to communicate simultaneously, addressing arbitration occurs.

Arbitration determines which device is allowed to communicate with the controller. For example, if devices A and B attempt simultaneous communication and have addresses 7'h10 and 7'h14 respectively, both will attempt to transmit their addresses to the active controller using open-drain signaling. During open-drain transmission, the line passively returns to '1' via pull-up and can be actively driven to '0'. The controller receives the address that wins arbitration. In I3C arbitration, a device attempting to transmit '1' will lose arbitration when another device actively drives '0', so higher address devices always lose to lower address devices in the illustrated scheme.

Summary

I3C increases serial bus bandwidth and introduces a range of new features, including dynamic addressing, in-band interrupts, secondary controllers, and HDR modes. This article covered the bus characteristics and key protocol concepts but is not an exhaustive list of features and commands. For full details, refer to the I3C specification and documentation provided by the MIPI Alliance.