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RZ/V2MA Vision AI Microprocessor Datasheet

Author : Adrian November 13, 2025

DRP-AI uses an AI accelerator composed of a dynamically reconfigurable processor (DRP) and AI-MAC. The accelerator speeds up AI inference to deliver high-performance inference with low power consumption, enabling real-time image AI processing without a heatsink or cooling fan. In addition, an OpenCV accelerator that leverages the high flexibility of DRP technology provides image preprocessing for AI inference and enables high-speed image processing beyond AI workloads on a single chip.

 

Features

  • Central processing unit (CPU) and double data rate (DDR) memory interface
  • Vision and AI
  • Video, graphics, and display
  • High-speed interfaces
  • One Gigabit Ethernet interface
  • One USB 3.1 Gen 1 host/device interface
  • One PCI Express (PCIe) Gen 2 interface (x2 lanes)
  • Two Secure Digital Input/Output (SDIO) 3.0 interfaces
  • One embedded multimedia card (eMMC) 4.5.1 interface
  • Package: flip-chip ball grid array (FCBGA), 15 × 15 mm, 0.5 mm pitch

RZ/V2MA block diagram

RZ/V2MA block diagram

Pin assignment

Pin assignment

Product lineup

Product lineup