Category:PCB PCB Layout

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The connections on a PCB should be identical to its corresponding circuit diagram, but while the circuit diagram is arranged to be readable, the PCB layout is arranged to be functional, so there is rarely any visible correlation.

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Analysis on the Layout of High-Speed Circuit Reply 2017-02-24 08:54:29


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PCB (printed circuit board) layout is critical to high-speed circuit. This article will explore the high-speed circuit layout in practical use, arousing the attention of beginners when layout the high-speed circuit as well as providing reference for reader who are not family with PCB layout. This article will emphasize on how to improve circuit performance, shorten design time and save time.
Though it focuses on circuit related to high-speed operation amplifier, all the issues and methods can be commonly used in other high-speed analog circuit. When the operation amplifier operates in a very high RF band, the performance of the circuit depends largely on PCB layout. Thus, pre-consideration and attention to important details throughout the layout will help ensure the expected circuit performance.
Excellent layout starts with good schematics. When drawing schematics, designers must be careful and take the flow of signals into consideration. If there is a normally stable signal flow from left to right in the schematic, the same good signal flow should also be present on the PCB. Besides, give useful information as much as possible on the schematic is helpful to solve the circuit problems when designers are not available.
In addition to the general reference identifier, power consumption and error tolerance, what information should be included on schematic? To follow these suggestions will make a common schematic into first-class one. For example, adding waveform, mechanical information, length of printed line and blank area; indicating components that should be placed on PCBs; offering adjustment information, component range, thermal information, control impedance line, notes, and brief circuit action description, etc.
Just like the PCBs, the location determines everything. It is important to decide the location that circuit on the PCB, specific circuit components other adjacent circuits should be.
Generally, the input, output and power supply locations are pre-determined. Starting with the location of the key components and depending on the specific circuit and the entire PCB, it is better to specify the location of key components and the path of the signal in the beginning, to ensure the expected design. Getting the right design once can reduce costs and stress as well as shorten the development cycle.
Bypass power supply
Bypass power supply on the power supply side of amplifier is important in PCB design, as well as high-speed operation amplifier and other high-speed circuits.
There are two common configuration methods.
Power Supply Ground: This is most effective in most cases, using parallel capacitors to ground the operation amplifier’s power supply directly. Generally speaking, two parallel capacitors are sufficient, but increasing the parallel capacitor may bring benefits to some circuits.
To connect capacitors with different capacitance helps to ensure that the power supply pin can only see low AC impedance in a wide frequency band. This is particularly important to operation amplifier PSR attenuation frequency. The capacitor helps to compensate for PSR reduced by amplifier. Keeping low impedance in many grounds within ten-times octaves will prevent harmful noise from amplifier. Figure 1 shows the advantages of parallel capacitors. In low frequency band, the large capacitor provides a low impedance ground. But once the frequency reaches their own resonant frequency, the capacitances are weakened and gradually appear inductive. This is why it is important to use parallel capacitors: when the frequency response of a capacitor begins to fall, the other capacitor begins its function, which can maintain very low AC impedance within ten-times octaves.

Figure 1. Relationship between Impedance and Frequency
Start directly from the operation amplifier’s power supply pins, capacitors with minimum capacitance and physical size should be placed on the same side of the PCB as the operation amplifier, as close as possible. The ground terminal of the capacitor should be connected directly to the ground plane with the shortest pin or line. The above ground connection should be as close as possible to the load side of the amplifier in order to reduce the interference between the power supply and the ground. Figure 2 shows this connection method.

Figure 2 Bypass Power Supply and Parallel Capacitors
The process should be repeated for capacitors with a large capacitance. It is best to start from the minimum capacitance of 0.01 μF and close to a 2.2 μF (or larger) electrolytic capacitor with a low equivalent series resistance (ESR). The 0.01 μF capacitor with a 0508 housing size has a low series inductance and excellent high frequency performance.
Power supply to power supply: Another configuration method applies one or more bypass capacitors across the op amp's positive and negative supply terminals. This is usually applied when four capacitors are difficult to configure in the circuit. Its drawback is that the size of the capacitor may be increased because the voltage across the capacitor is twice the voltage value in the single bypass power supply. Voltage increase requires increasing the device's rated breakdown voltage, which is to increase the size. However, this method can improve PSR and distortion performance.
Because each circuit and layout is different, so the capacitor configuration, quantity and capacitance should be based on the actual circuit requirements.
Parasitic effects
The so-called parasitic effects refer to the unknown small fault in your PCB, which cause great damage to circuit. They are hidden parasitic capacitance and parasitic inductance that infiltrated into the high-speed circuit, which include the parasitic inductance formed by the package pins and the printed line; the parasitic capacitance formed between the pads to the ground, the pads to the power plane and the pads to the printed lines; the interaction between the vias, and other possible parasitic effects. Figure 3 (a) shows a typical in-phase op amp schematic. However, if the parasitic effect is taken into account, the same circuit may become as shown in Figure 3 (b).

Figure 3 (a) Typical OP AMP Schematic

Figure 3 (b) Schematic with Parasitic Effect
In the high-speed circuit, a small value will affect the circuit performance. Sometimes dozens of pF capacitor is enough. For example, if there is only 1 pF of additional parasitic capacitance at the inverting input, it can cause almost 2 dB of spike pulse in the frequency domain (see Figure 4). If the parasitic capacitance is large enough, it can cause instability and oscillation of the circuit.

Figure 4 Additional Spike Pulse Caused by Parasitic Capacitance
When looking for a problematic parasitic source, it may be possible to use several basic formulas for calculating the parasitic capacitance dimensions described above. Formula (1) is for calculating the parallel plate capacitor (see Figure 5).

Formula (1)
C: Capacitance value, A: plate area in cm2, k: relative permittivity of the PCB material, d: distance between the plates in cm.

Figure 5 Capacitance between Bipolar Plates
Band inductance is another parasitic effect that needs to be considered, which is caused by too long trace or a lack of a ground plane. Formula (2) is for calculating the inductance of trace. See Figure 6.

Formula (2)
W: Trace width, L: Trace length, H: Trace thickness. All dimensions are in mm.

Figure 6 Inductance of Trace
The oscillation in Figure 7 shows the effect of a high-speed op amp with a non-inverting input length of 2.54 cm. The equivalent parasitic inductance is 29 nH (10-9H), enough to cause sustained low voltage oscillation, will continue to the entire transient response cycle. Figure 7 also shows how the ground plane can be used to reduce the effect of parasitic inductance.

Figure 7 Impulse Response with/without Ground Plane
The vias are another parasitic source; they can cause parasitic inductance and parasitic capacitance. Formula (3) is for calculating the parasitic inductance (see Figure 8).

Formula (3)
T: PCB thickness, d: diameter of the vias in cm.

Figure 8 Via size
Formula (4) shows how to calculate the parasitic capacitance value caused by vias (see Figure 8).

Formula (4)
εr: Relative permeability of the PCB material, T: PCB thickness, D1: Pad diameter around the through hole, D2: Diameter of the isolation hole in the ground plane. All dimensions are in cm. A via in the 0.157cm thick PCB can increase 1.2nH parasitic inductance and 0.5 pF parasitic capacitance. That’s why we should minimize the impact of parasitic effects in PCB layout.
Ground plane
The ground plane acts as a common reference voltage, providing shielding, capable of cooling and reducing parasitic inductance. Although there are many benefits of ground plane, but designers must be careful when it is implemented because it has some limitations.
Ideally, a layer of PCB should be used exclusively as a ground plane so that it will produce the best results when the whole plane is not destroyed. Do not divert the area of the ground plane in this dedicated layer for connecting other signals. Since the ground plane can eliminate the magnetic field between the conductor and the ground plane, the inductance of trace can be reduced. If a region of the ground plane is destroyed, an unexpected parasitic inductance is introduced into the ground plane above or below the ground plane.
The resistance of the ground plane should be kept to a minimum because the ground plane usually has a large surface area and cross-sectional area. In the low frequency band, the current selects the path with the least resistance while the current selects the path with the least impedance in the high frequency band.
However, there are exceptions, and sometimes a small ground plane will be better. If the ground plane is removed from the input or output pad, the high-speed op amp will work better. Because the parasitic capacitance introduced at the input ground plane increases the input capacitance of the op amp and reduces the phase margin, resulting in instability.In the section of the parasitic effects, the 1 pF capacitor at the input of the op amp can cause sharp pulses. The capacitive load at the output, including the parasitic capacitive load, causes the poles in the feedback loop. This will reduce the phase margin and cause the circuit to become unstable.
If possible, analog circuits and digital circuits, including the respective ground and ground planes, should be separated. A fast rising edge can causes the current burr to flow into the ground plane. The noise caused by these fast current burrs can damage the simulation performance. Analog ground and digital ground (and power supply) should be connected to a common ground point in order to reduce the current and noise of circulating digital and analog ground.
In the high frequency band, a phenomenon called "skin effect" must be considered. The skin effect will causes the current to flow to the outer surface of the wire, narrowing the cross-section of the wire and increasing the DC resistance. Although the skin effect is beyond the scope of this article, there is a good approximate formula (in cm) for the Skin Depth in the copper wire:

Formula (5)
Less sensitive plated metal helps to reduce the skin effect.
Operation amplifiers are usually in different packages. The selected package will affect the high frequency performance of the amplifier. The main effects include parasitic effects (previously mentioned) and signal paths. Here we focus on the amplifier's path input, output and power supply.
Figure 9 shows the layout differences between the operation amplifiers using the SOIC package (a) and the SOT-23 package (b). Each package has its own problems. Focus on (a), carefully observe the feedback path, you will find a variety of ways to connect feedback. The most important thing is to ensure that the minimum length of trace. Parasitic inductance in the feedback path can cause ringing and overshoot. In Figure 9 (a) and 9 (b), the surround amplifier is connected to the feedback path. Figure 9 (c) shows another method is to connect the feedback path below the SOIC package, thus reducing the length of the feedback path. Each method has a slight difference. The first method will lead to too long trace and increase the series inductance. The second method applies vias that can cause parasitic capacitance and parasitic inductance.
The effects of these parasitic effects and their implicit problems must be taken into account in PCB layout. SOT-23 layout difference is almost the best: the feedback line is the shortest, and rarely uses the vias; load and bypass capacitor return to the same ground connection in a very short path; capacitor on positive power supply side (Not shown in Figure 9 (B)) is placed directly below the negative power supply capacitor on the back of the PCB.

Figure 9 Layout difference in same op amp circuit, (a) SOIC package, (b) SOT-23 package, (c) RF SOIC package under PCB
Pinout of low-distortion amplifiers: Some op amps provided by ADI (such as the AD80451) feature a new low-distortion pinout to help eliminate the two issues mentioned above. And it also improves the performance on other two important aspects. LFCSP's low-distortion pinout, as shown in Figure 10, moves the traditional op amp's pinout in a counter-clockwise direction and adds an output pin as a dedicated feedback pin.

Figure 10 op amps with low-distortion pinout
The low distortion pinout allows the output pin (dedicated feedback pin) and the inverting input pin to be close to be connected, as shown in Figure 11. This greatly simplifies and improves layout.

Figure 11 PCB layout of AD8045 low-distortion op amps
Another advantage of this pinout is to reduce the second harmonic distortion. One reason for the second harmonic distortion in the pin configuration of a conventional op amp is the coupling between the in-phase input and the negative supply pin. The low distortion pinout of the LFCSP package eliminates this coupling and greatly reduces the second harmonic distortion; in some cases, it can be reduced by up to 14 dB. Figure 12 shows the distortion performance difference of AD80992 using SOIC package and LFCSP package.
This package also has a benefit - low power consumption. The LFCSP package has a bare pad, which reduces the thermal resistance of the package, improving the θJA value by about 40%. Because the thermal resistance is reduced, the operating temperature of the device is reduced, which is equivalent to improving the reliability.

Figure 12 Distortion Performance Comparison of AD8099 with Different Packaging
At present, ADI offers three high-speed op amps with the new low-distortion pins: AD8045, AD8099 and AD80003.
Layout and shield
A wide variety of analog and digital signals exist on PCBs, ranging from high to low voltage or current from DC to GHz frequency range. It is very difficult to ensure that these signals do not interfere with each other.
The most critical thing is to think ahead and make a plan for how to handle the signals on the PCB. It is important to note which signals are sensitive and determine what measures must be taken to ensure signal integrity. The ground plane provides a common reference point for the electrical signal and can also be used for shield. If signal isolation is required, the physical distance should first be left between the signal trace. Here are some practical lessons that are worth learning from:
1. Reduce the length of the long parallel traces in the same PCB and the proximity between the signal lines can reduce the inductance coupling.
2. Reduce the length of the long adjacent layers trace can prevent capacitive coupling.
3. Signals traces that require high isolation should take different layers and the orthogonal traces should be taken and the ground planes should be placed between them if they cannot be completely isolated. Orthogonal layout minimizes capacitive coupling, and the ground forms an electrical shield. This method can be used when forming a control impedance trace.
4. High frequency (RF) signals typically flow on the control impedance trace. That is, the trace maintains characteristic impedance, such as 50Ω (typical in RF applications). Two of the most common control impedance traces, microstrip traces 4 and stripline 5 can achieve similar effects with different methods.
The microstrip control impedance trace, as shown in Figure 13, can be used on either side of the PCB; it uses its underlying ground plane as its reference plane.

Figure 13 Microstrip Traces
Formula (6) is for calculating the characteristic impedance of an FR4 board.

Formula (6)
H: Distance from the ground plane to the signal trace, W: Trace width, and T: Trace thickness; all dimensions are in mils (10-3 in.).εr: Dielectric constant of the PCB material
The stripline control impedance trace (see Figure 14) uses a two-layer ground plane in which the signal line is clamped. This method uses many traces and requires more PCB layers, sensitive to changes in dielectric thickness. And it is more costly so that it is usually used only in applications with strict requirements.

Figure 14 Stripline Control Impedance Trace
Characteristic impedance calculation formula for the stripline is shown in formula (7).

Formula (7)
Protection ring, or "isolation ring", is another op amp commonly used shielding method, preventing parasitic current into the sensitive nodes. The basic principle is very simple - with a protective wire to completely enclose the sensitive nodes, the wire to keep or force it to maintain same potential with sensitive nodes, so that the absorbed parasitic current away from the sensitive nodes. Figure 15 (a) shows a schematic diagram of a protection ring for inverting configuration and in-phase configuration of the op amp. Figure 15 (b) shows two typical layout methods for protection rings in the SOT-23-5 package.

Figure 15 Protection Ring, (a) Inverting and In-phase Configuration, (b) SOT-23-5 Package
High-level PCB layout is important for successful op amp circuit design, especially for high-speed circuits. A good schematic is the basis for good layout. The close cooperation between the circuit design engineer and the layout design engineer is fundamental, especially with regard to the location of the device and wiring. Issues should be considered include bypass power, to reduce parasitic effects, the use of ground plane, the effects of op amp package, and layout and shielding methods.
Statement: This post is only the personal view of the author and does not represent the opinions of


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