There are many ways to solve the EMI problem. The modern EMI suppression methods include: EMI suppression coating, appropriate EMI suppression parts and EMI simulation design, etc. We will discuss the role and design techniques of PCB stack-up in controlling EMI radiation.
Power supply bus
Placing appropriate capacity near to the IC power supply pin, the IC output voltage jump will happen soon. However, the problem is not so far. Since the capacitor has a characteristic of limited frequency response, which makes it impossible to generate the harmonic power required to drive the IC output in a full frequency band. In addition, the transient voltage formed on the power supply bus creates a voltage drop across the inductor at both ends of the decoupling trace. These transient voltages are the main common mode EMI sources. How should we solve these problems?
For the ICs on our circuit boards, the power supply layer around the IC can be regarded as an excellent high-frequency capacitor that collects the amount of energy that is leaking from discrete capacitors that provide high-frequency energy for clean output. Besides, the excellent power supply layer inductance should be small, so the transient signal created by inductance is also small, thereby reducing the common mode EMI.
Of course, the connection from the power supply layer to the IC power supply pin must be as short as possible because the rising edge of the digital signal is faster and faster, and it is best to connect directly to the pad where the IC power supply pin is located.
In order to control the common mode EMI, the power layer will help decouple and have a sufficiently low inductance, which must be a well-designed power layer. Some people may ask how good is acceptable? The answer to the problem depends on the lamination of the power supply, the material between layers, and the operating frequency. Typically, 6 mils supply spacing and FR4 interlayer, the equivalent capacitance per square inch of the power supply layer is about 75pF. Obviously, the smaller interlayer spacing has larger capacitance.
There are few devices with a rise time of 100 to 300 ps,but deviceswith high rise times in the range of 100 to 300ps will have a high percentage according to the current IC development speed. For circuits with a rise time of 100 to 300 ps,the 3 mil layer spacing will no longer apply to most applications.At that time, it is necessary to use layer spacing of less than 1mil layered technology, and with a high dielectric constant material instead of FR4 dielectric material. Now, ceramic and pottery plastic can meet the design requirements of the 100 to 300ps rise time circuit.
Although new materials and new methods may be used in the future, for today's common circuits with 1 to 3 ns rise time, 3 to 6 mil layer spacing and FR4 dielectric materials are sufficient to handle high-end harmonics and make the transient signal low enough. Otherwise, the common mode EMI can drop very low. The PCB stack-up design example will assume a layer spacing of 3 to 6 mils.
A good lamination strategy should put all the signal traces on a layer or multi layers that is next to the power layer or ground plane. For power supply, a good lamination strategy should be the power layer adjacent to the ground layer and spacing between power layer and the ground layer as small as possible.
What kind of stack-up strategy helps to shield and suppress EMI? The following stack-up methods scheme assume that the supply current flows on a single layer, and that a single voltage or multiple voltage is distributed across different parts of the same layer.
There are several potential problems with 4-layer board design. First, the traditional thickness of 62mil four-layer board, even if the signal layer in the outer layer, power and ground layer in the inner layer, the power supply layer and the ground layer spacing is still too large.
If the cost is prioritized, designers can consider the following two traditional 4-layer alternatives. Both of these solutions improve EMI suppression performance if the board component density is low enough and there is sufficient area around the component.
The first is the preferred solution, the outer layers of the PCB are ground layers, and the middle two layers are signal or power layer. The power supply on the signal layer apply wide traces, which makes the trace impedance of the supply current low and the impedance of the signal microstrip trace is low. From the EMI control, this is the best existing 4-layer PCB structure. In the second solution, the outer layers are power and ground layer, the middle two layers are the signal. The solution makes less improvement than the traditional 4-layer board, and the interlayer impedance is as bad as the traditional 4-layer board.
If you want to control the trace impedance, the above stack-up solution should carefully place traces below copper-spread island of the power supply and ground layer. In addition, copper-spread island on the power or ground layer should be interconnected as much as possible to ensure connectivity between DC and low frequency.
If the component density on the 4-layer board is relatively large, it is preferable to use a 6-layer board. However, some of the stack-up solution in the 6-layer board design is not good enough for the shielding of the electromagnetic field, which has little effect on the reduction of the transient signal of the power supply bus. Two examples are discussed below.
The first example of the power and ground were placed on the 2nd and 5th layers. Due to the high resistance of power supply copper, the control of common mode EMI radiation is very negative. However, from the signal impedance control, this method is very correct.
The second example places the power supply and ground on the 3rd and 4th layers, and this design solves the problem of resistance of power supply copper. Since the electromagnetic shielding performance of the first and sixth layers is poor, the differential mode EMI is increased. This design solves the differential mode EMI problem if the number of signal lines on both outer layers is the least and the trace length is very short. The suppression of the differential mode EMI is particularly good by filling the non-components and non-traces of the outerlayer with copper and grounding the copper area. As mentioned earlier, the copper area should be multipoint connected to the internal ground plane.
General high-performance 6-layer boards design generally takes the first and sixth layer as ground, and the third and fourth layers are power and ground layers. Since the dual microstrip signal layer centered between the power supply layer and the ground layer, the EMI suppression is excellent. The weak point of this design is that there are only two layers of the trace. As mentioned above, if the outer traces are short and fill copper on the non-trace area, the same stack-up can also be achieved with a conventional 6-layer board.
Another 6-layer board layout order is signal, ground, signal, power, ground, signal, which can achieve required environment for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power supply layer and the ground plane are paired. Obviously, the downside is that the stack-ups are unbalanced.
This usually causes trouble in manufacture. The solution to the problem is to fill all the blank areas of the third layer with copper. After filling copper, if the copper density of third layer is close to the power layer or ground layer, the board cannot be strictly counted as a circuit board with balanced structure. The copper-filled area must be connected to the power supply or ground. The distance between vias is still 1/20 wavelength, not necessarily connected everywhere, but ideally should be connected.
Since the insulation isolation layer between the multilayer boards is very thin, the impedance between the circuit board layers of the 10 or 12 layers is very low. Excellent signal integrity is expected to be achieved as long as there is no problem with lamination and stack-up. Manufacturing 12-layer board with the thickness of 62mil is more difficult because 12-layer board manufacturers are not many.
There is always an insulating layer between the signal layer and the circuit layer, thus it is not optimal to allocate the middle 6 layers for signal in the 10-layer board design. In addition, it is important that the signal layer and the circuit layer are adjacent, that is, the board layout order is signal, ground, signal, signal, power, ground, signal, signal, ground, and signal.
This design provides a good trace for the signal current and its loop current. The proper layout strategy is that the first layer is traced along the X direction, the third layer is traced along the Y direction, and the fourth layer is traced along the X direction, and so on. Intuitive to see the trace, the first layer and the third layer is a pair of layered combination, the fourth and seventh layer is a pair of layered combination, while the eighth and tenth layer is the last pair of layered combination. When the trace direction needs to be changed, the signal trace on the first layer should be changed by "via" to the third layer. In fact, it may not always be done, but to follow as a design concept.
Similarly, when the signal traces direction changes, it should be changed by "via" from the 8th layer to 10th layer or from the 4th to 7th layer. This layout ensures that the coupling between the forward trace and the signal loop is tightest. For example, if the signal is placed on layer 1 and the loop is only on layer 2, the loop is still on the layer 2 when the signal on layer 1 is transferred to layer 3 by "vias", thus maintaining low inductance, large capacitance and good electromagnetic shielding performance.
What we should do if the actual layout is not the case? For instance, when the signal trace on the first layer connect to the 10th layer by “vias”, the loop signal had to connect to ground through the 9th layer and loop current should connect to the closest ground vias (such as the ground pin of resistors or capacitors). If there is no such vias available, the inductance will become larger, the capacitance will be reduced, EMI will definitely increase.
When the signal trace must current pair of layout layer to the other layout layer by vias, designers should place ground vias near to those vias, so that the circuit signal can be successfully returned to the appropriate ground layer. For the layered combination of layer 4 and layer 7, the signal loop will return from the power layer or ground layer because the capacitive coupling between the power supply layer and the ground layer is good and the signal is easy to transmit.
Multi power layer design
If the two power supply layers with same voltage source need to output high current, the circuit board should be placed with two pair of power supply layer and ground layer. In this case, an insulating layer should be placed between each pair of the power supply layer and the ground layer. This gives us the desired two pairs of power supply bus with equal current and equal impedance. If the stack-up of the power supply causes the unequal impedance, the shunt is not uniform, the transient voltage will be much larger, and the EMI will increase dramatically.
If there are multiplesupply voltages with different valueson the board, multiple power layers are required accordingly. And the different power supply layers and ground layers should be created for different power sources. In both cases above, to keep the manufacturer's requirements for the balanced structure in mind when match power supply layer and the ground layer.
The discussion of circuit board lamination and stack-up is limited because most engineers design circuit boards with a conventional printed circuit board with a 62 mil thickness, without blind or buried vias. The proposed lamination solutions may not be ideal for the circuit board with large thickness difference. Besides, the lamination method is not applicable for with the blind or buried vias.
The thickness, vias process and the number of layers is not the key to solve the problem in PCB design. The excellent stack-up ensures the bypass and decoupling of the power supply bus so that the transient voltage on the power supply layer or ground layer is the smallest and the electromagnetic field of signal and power can be shielded. Ideally, there should be an insulation barrier between the signal trace layer and its loop grounded layer, and the paired layer spacing should be as small as possible. According to these basic concepts and principles, you are able to meet the design requirements of the circuit board all the time. Now, IC's rise time is very short and will be shorter, the discussed technology to solve the EMI shielding is essential.
Statement: This post is only the personal view of the author and does not represent the opinions of ALLPCB.com.