ONFI: NAND Flash Interface Explained
Explore the ONFI standard for NAND Flash: interface specs, data rates, NV-LPDDR4 advances, signal integrity challenges and simulation techniques.
Explore the ONFI standard for NAND Flash: interface specs, data rates, NV-LPDDR4 advances, signal integrity challenges and simulation techniques.
Explore SRAM scaling limits, SRAM vs DRAM trade-offs, chiplet and alternative memory strategies, and architectures to meet AI memory demands.
Guide to NAND, DDR/LPDDR, eMMC vs UFS and eMCP/uMCP: memory types, uses, performance and trends for mobile, enterprise and storage.
Explore memory-compute integration: PIM/PNM/CIM advantages, industry players, startup innovations, and market potential for energy-efficient AI chips.
Explore SRAM storage capacity, key characteristics, advantages, and applications like cache memory in this detailed guide.
Explains DDR5 subchannels: splitting 64-bit DIMMs into two 32-bit subchannels so BL=16 yields 64-byte transfers matching CPU cache lines.
3D NAND fabrication: substrate prep, stacked oxide/nitride layers, channel via & slit etch, TiN/W fill, polysilicon channels and metal bitlines
Weebit Nano and DB HiTek integrate ReRAM into a 130 nm BCD process for PMICs, enabling BEOL monolithic integration, lower mask count, and energy-efficient NVM.
Technical overview of MySQL architecture and SQL optimization, covering index types (B+ tree), index creation, EXPLAIN execution plan analysis, and practical optimization tips.
China SSD market overview: trends, classifications, supply chain, market size, growth forecasts and competitive landscape.