9 Types of Computer Memory and How They Work
Computer memory explained: primary vs secondary, volatile vs nonvolatile, RAM, ROM, HDDs and SSDs - uses and trade-offs.
Computer memory explained: primary vs secondary, volatile vs nonvolatile, RAM, ROM, HDDs and SSDs - uses and trade-offs.
HBM3E boosts AI training with 9.6 Gb/s bandwidth, offering high performance and efficiency for accelerators and GPUs.
Learn why DRAM requires refreshing, its structure, and how it differs from SRAM in this detailed guide to memory technology.
Comprehensive guide to memory chips: DRAM, NAND flash, RAM vs ROM, storage hierarchy, NAND types, DRAM families, supply chain and industry models
Photonic interconnects by Celestial AI aim to solve AI memory bottlenecks with optical fabric and chiplets for enhanced bandwidth.
Explore the memory hierarchy in computers, its design purpose, and how it balances speed, capacity, and cost effectively.
HBM4 overview: principles, advantages, applications and trends in high-bandwidth memory for AI, HPC, and data centers.
Overview of DMA architecture, modes, registers, and configuration on STM32 microcontrollers, covering transfer types, channels, interrupts, and DMA controller usage.
DRAM testing and inspection challenges: wafer-level screening, DFT, high-speed interfaces, HBM multi-chip packaging, yield and reliability.
Deep dive DDR vs SDRAM internals: block diagrams, differential clock/DQS, DLL, 2n prefetch, tDQSS, mode registers and timing differences.
Explore the ONFI standard for NAND Flash: interface specs, data rates, NV-LPDDR4 advances, signal integrity challenges and simulation techniques.
Explore SRAM scaling limits, SRAM vs DRAM trade-offs, chiplet and alternative memory strategies, and architectures to meet AI memory demands.
Explore memory-compute integration: PIM/PNM/CIM advantages, industry players, startup innovations, and market potential for energy-efficient AI chips.
Guide to NAND, DDR/LPDDR, eMMC vs UFS and eMCP/uMCP: memory types, uses, performance and trends for mobile, enterprise and storage.
Explore SRAM storage capacity, key characteristics, advantages, and applications like cache memory in this detailed guide.
Explains DDR5 subchannels: splitting 64-bit DIMMs into two 32-bit subchannels so BL=16 yields 64-byte transfers matching CPU cache lines.
Weebit Nano and DB HiTek integrate ReRAM into a 130 nm BCD process for PMICs, enabling BEOL monolithic integration, lower mask count, and energy-efficient NVM.
3D NAND fabrication: substrate prep, stacked oxide/nitride layers, channel via & slit etch, TiN/W fill, polysilicon channels and metal bitlines
Technical overview of MySQL architecture and SQL optimization, covering index types (B+ tree), index creation, EXPLAIN execution plan analysis, and practical optimization tips.
China SSD market overview: trends, classifications, supply chain, market size, growth forecasts and competitive landscape.