Why DDR5 Is So Stable

Explore DDR5 reliability: how RAS features, on-die ECC, DCA, DQS oscillator, CRC and DFE, enable stable high-speed memory.

Debunking Myths About DRAM Market Trends

DRAM trends: sustained multiplicative scaling, rising density and per-die capacity, and evolving I/O strategies (HBM, GDDR, DDR, LPDDR) 2010s-2020s

DirectCXL: Directly-Accessible Disaggregated Memory

DirectCXL uses CXL.mem to access disaggregated memory with load/store semantics, reducing latency vs RDMA up to 8.3× and improving real workloads ~3×.

Understanding Memory Hierarchy Principles

Explore memory hierarchy, cache basics, locality principles, and practical tips for writing cache-friendly code to boost performance.

Types and Advantages of NAND Storage

Explore memory chip types, NAND flash benefits, serial vs raw NAND differences, and SIDesigner simulation tips for NAND flash modeling.

Memory-to-Peripheral DMA Techniques

DMA explained: offload the CPU for efficient memory-to-peripheral and peripheral-to-memory transfers, buffering, ADC/DAC pipelines, and concurrency.

How DMA Enables Direct Data Transfer

Learn how DMA enables direct peripheral-to-memory transfers, reducing CPU involvement in I/O on Linux and improving system efficiency.

SD Card Types and Attributes for Embedded Systems

Comprehensive SD card guide: speed classes, capacities, form factors, SD/SPI interfaces, protocol and hardware design tips for reliable integration.

TigerGraph 108TB LDBC Benchmark Analysis

TigerGraph's 108TB LDBC SNB BI benchmark: 217.9B vertices, 1.6T edges, OLAP query performance, scalability, and infrastructure insights.

Understanding MRAM Principles and Technology

MRAM: non-volatile memory with SRAM-like speed, DRAM density and virtually unlimited endurance using magnetic tunnel junctions.

Why DDR5 DIMMs Use Two Subchannels

Explains DDR5 subchannels: splitting 64-bit DIMMs into two 32-bit subchannels so BL=16 yields 64-byte transfers matching CPU cache lines.

9 Types of Computer Memory and How They Work

Computer memory explained: primary vs secondary, volatile vs nonvolatile, RAM, ROM, HDDs and SSDs - uses and trade-offs.

3D NAND Channel Hole Etching Steps

Channel hole formation and high-aspect-ratio etching for stacked memory: amorphous carbon mask, ICP/CCP RIE, control of diameter, sidewalls and depth.

3D NAND Fabrication Process Overview

3D NAND fabrication: substrate prep, stacked oxide/nitride layers, channel via & slit etch, TiN/W fill, polysilicon channels and metal bitlines

What Is Phase-Change Memory and How to Characterize It

Phase-change and PCM explained: GST materials, SET/RESET pulse programming, electrical characterization and test setups for PCM devices.

Resistive Memory: Architecture and Applications

Explore RRAM: fast, low-power resistive memory for neuromorphic computing, in-memory acceleration, and scaling, retention and variability challenges.

HBM Technology: Principles and Advantages

HBM4 overview: principles, advantages, applications and trends in high-bandwidth memory for AI, HPC, and data centers.

JesFS Flash File System for Small Controllers

JesFS: tiny, reliable embedded file system for ultra-low-power devices, small RAM/flash footprint, robust logging, remote sync and safe updates.

How Flash Memory Stores Data

Learn how computers store data in binary, how flash memory's floating-gate transistors work, and flash endurance and wear-leveling.

Korean team develops ultra-low-power phase-change memory

KAIST demos ultra-low-power phase-change memory using self-confined nano-filament, 15x lower power and lithography-free for neuromorphic AI.