EDA Industry Evolution and Major Vendors

EDA overview: tools, major global and Chinese vendors, and key chip design and manufacturing tool categories.

Chip Design and Tapeout: Key Processes Explained

Guide to chip tapeout, design, verification, fabrication and costs. Covers tapeout modes, ECOs, corners, pricing and production readiness.

What Does Advanced-Process Chip Design Cost?

Why chip development costs may be lower than claimed: design simplification, advanced packaging, delayed node migration, software and EDA impacts.

Chip Packaging: 3D Stacking to Overcome the Memory Wall

Explore memory area growth in modern CCDs: AMD 3D V-Cache, stacked SRAM, HBM tradeoffs, Intel base-layer architectures and thermal impacts.

Why the Semiconductor Industry Is Replacing FinFET

Explore how nanosheet (GAA) transistors and 3D chip stacking complement FinFET scaling, driving 2-3nm node advances and chiplet integration.

Metastability and Synchronizers in Chip Design

Learn metastability, MTBF, and synchronizer techniques for safe clock-domain crossings in multi-clock chip designs.

EDA Design Flow: Key Steps and Common Tools

EDA design flow explained: planning, circuit design, simulation, layout, verification, timing & power optimization, key tools and HDLs.

Fundamentals of IC Layout

Learn N-well and CMOS layout fundamentals: N-well function, active areas, poly1 gates, diffusion, contacts, metals, vias and simple inverter layers.

Verification: the Heavy Burden in SoC Design

SoC design and verification: EDA tools, tapeout flows, power/security and scalability challenges, and gaps in China’s EDA.

Introduction to Asynchronous FIFO in Digital IC Design

Learn asynchronous FIFO design for clock-domain crossing: write/read pointers, Gray-code synchronization, and robust full/empty detection.