ALLPCB
SoC DFT Strategies and Full-Chip Testing Overview
Technical overview of SoC DFT: scan-based tests, BIST/MBIST, ATPG, boundary-scan, fault models and DFT flow considerations for large system-on-chip designs.
EMC: Electromagnetic Shielding Notes
Antenna models (loop, dipole), near/far-field radiation and shielding effectiveness: reflection, absorption, and practical EM shielding tips.
Chip Performance: Time Parallelism
Learn PPA trade-offs and chip performance: bandwidth, throughput, latency explained with AXI, outstanding transactions, buffering and pipelining.
Digital IC Front-End Design Flow and Tools
Gate-level netlist guide: synthesis, simulation, DFT, formal verification and STA for front-end/back-end design.
Modern Electronic Integration: Scales and Dimensions
Explore electronic integration: scales from particles to systems, dimensions (2D-4D), and IC trends toward smaller scales and higher dimensions.
Voltage Reference ICs with Noise-Reduction Pins
Reduce voltage reference noise with TRIM/noise pins (TI REF50xx), external caps, ESR tips or precision op-amp filters. Consult datasheet.
Overview of UVM for Digital IC Verification
Learn Coverage-Driven Verification (CDV) with UVM: testbench architecture, constrained-random testing, coverage collection, simulation and reuse.
QSPICE Enhances Power Design Efficiency
QSPICE boosts power design efficiency with advanced digital and analog simulation for cutting-edge projects in AI and electric vehicles.
Yingnuoda Low-Power EDA Full-Flow Solution
Yingnuoda's low-power EDA tools (LPC, RPA, GPA) enable early RTL power estimation and optimization across the IC design flow.
3D Perspective for Integrated Circuit Design
Explore Cubic IC 3D design: stacking storeys, EDA tool needs, LITS, EFV, manufacturing and thermal challenges for future ICs.