ALLPCB
SoC DFT Strategies and Full-Chip Testing Overview
Technical overview of SoC DFT: scan-based tests, BIST/MBIST, ATPG, boundary-scan, fault models and DFT flow considerations for large system-on-chip designs.
EMC: Electromagnetic Shielding Notes
Antenna models (loop, dipole), near/far-field radiation and shielding effectiveness: reflection, absorption, and practical EM shielding tips.
Chip Performance: Time Parallelism
Learn PPA trade-offs and chip performance: bandwidth, throughput, latency explained with AXI, outstanding transactions, buffering and pipelining.
Digital IC Front-End Design Flow and Tools
Gate-level netlist guide: synthesis, simulation, DFT, formal verification and STA for front-end/back-end design.
Modern Electronic Integration: Scales and Dimensions
Explore electronic integration: scales from particles to systems, dimensions (2D-4D), and IC trends toward smaller scales and higher dimensions.
Voltage Reference ICs with Noise-Reduction Pins
Reduce voltage reference noise with TRIM/noise pins (TI REF50xx), external caps, ESR tips or precision op-amp filters. Consult datasheet.
Overview of UVM for Digital IC Verification
Learn Coverage-Driven Verification (CDV) with UVM: testbench architecture, constrained-random testing, coverage collection, simulation and reuse.
Yingnuoda Low-Power EDA Full-Flow Solution
Yingnuoda's low-power EDA tools (LPC, RPA, GPA) enable early RTL power estimation and optimization across the IC design flow.
QSPICE Enhances Power Design Efficiency
QSPICE boosts power design efficiency with advanced digital and analog simulation for cutting-edge projects in AI and electric vehicles.
3D Perspective for Integrated Circuit Design
Explore Cubic IC 3D design: stacking storeys, EDA tool needs, LITS, EFV, manufacturing and thermal challenges for future ICs.
Common EDA Input Methods, Development Stages, and Goals
EDA overview: input methods, development stages, and goals to automate circuit design, simulation, verification, and system-level integration.
Pipeline Design: Key Points
Pipeline design: temporal parallelism, stage partitioning, throughput vs. latency trade-offs, and backpressure handling for efficient hardware.
Verilog Design Guidelines Overview
Verilog guidelines for readable, efficient IC design: coding practices, module instantiation, operators, and module design templates.
What IP and EDA Tools Do IC Designs Need?
Explore IC design challenges: 3DIC & chiplet interconnects, EDA/IP needs, edge processors, RISC-V evolution and China's EDA/IP integration.
Chip Power Control and Verification Methods
Explore chip power consumption sources and low-power design techniques, clock gating, DVFS, power gating, multi-voltage and layout optimizations.
Challenges Facing the IC Design Industry
Weak semiconductor demand pressures driver ICs: analysts warn falling prices, shrinking margins and weak Q3 amid rising capacity and competition.
Basic TLM Communication for Digital IC Verification
Learn UVM TLM basics: building transactions, and using blocking put/get ports and exports for producer/consumer communication.
Challenges in IC Design
Practical RTL design tips: implementable RTL, AXI master strategies, timing/pipelining, area, power and backend-aware coding for performance.
How Changing Workloads Reshape Chip Architecture
Explore how architecture-driven chip design, in-memory compute, co-packaging and scalable interconnects boost performance and efficiency.
Chip Design Process and 5G Chip Design Challenges
Explore the chip design process from requirements to production and learn key 5G challenges: complexity, power, RF, packaging, and security.