Low-Power Techniques in IC Design and Design Flow

Low-power IC design techniques—voltage/clock management, power gating, sleep modes—and IC design flow from front-end to mass production.

Types of EDA Synthesis and Logic Synthesis Principles

EDA synthesis: converting HDL into optimized logic netlists. Learn types—logic, timing, physical, and power optimization—for IC design.

IC Chip Design with Copper Interconnects

Learn how copper interconnects, low-k dielectrics, SOI, and HKMG enable reliable, high-performance 32/28nm CMOS scaling and advanced lithography.

Overview of UVM for Digital IC Verification

Learn Coverage-Driven Verification (CDV) with UVM: testbench architecture, constrained-random testing, coverage collection, simulation and reuse.

Pipeline Design: Key Points

Pipeline design: temporal parallelism, stage partitioning, throughput vs. latency trade-offs, and backpressure handling for efficient hardware.

Yingnuoda Low-Power EDA Full-Flow Solution

Yingnuoda's low-power EDA tools (LPC, RPA, GPA) enable early RTL power estimation and optimization across the IC design flow.

Digital IC Front-End Design Flow and Tools

Gate-level netlist guide: synthesis, simulation, DFT, formal verification and STA for front-end/back-end design.

3D Perspective for Integrated Circuit Design

Explore Cubic IC 3D design: stacking storeys, EDA tool needs, LITS, EFV, manufacturing and thermal challenges for future ICs.

Fundamentals of IC Layout

Learn N-well and CMOS layout fundamentals: N-well function, active areas, poly1 gates, diffusion, contacts, metals, vias and simple inverter layers.

Basic TLM Communication for Digital IC Verification

Learn UVM TLM basics: building transactions, and using blocking put/get ports and exports for producer/consumer communication.