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EDA Industry Evolution and Major Vendors
EDA overview: tools, major global and Chinese vendors, and key chip design and manufacturing tool categories.
Chip Design and Tapeout: Key Processes Explained
Guide to chip tapeout, design, verification, fabrication and costs. Covers tapeout modes, ECOs, corners, pricing and production readiness.
Why the Semiconductor Industry Is Replacing FinFET
Explore how nanosheet (GAA) transistors and 3D chip stacking complement FinFET scaling, driving 2-3nm node advances and chiplet integration.
What Does Advanced-Process Chip Design Cost?
Why chip development costs may be lower than claimed: design simplification, advanced packaging, delayed node migration, software and EDA impacts.
Chip Packaging: 3D Stacking to Overcome the Memory Wall
Explore memory area growth in modern CCDs: AMD 3D V-Cache, stacked SRAM, HBM tradeoffs, Intel base-layer architectures and thermal impacts.
Metastability and Synchronizers in Chip Design
Learn metastability, MTBF, and synchronizer techniques for safe clock-domain crossings in multi-clock chip designs.
EDA Design Flow: Key Steps and Common Tools
EDA design flow explained: planning, circuit design, simulation, layout, verification, timing & power optimization, key tools and HDLs.
Introduction to Asynchronous FIFO in Digital IC Design
Learn asynchronous FIFO design for clock-domain crossing: write/read pointers, Gray-code synchronization, and robust full/empty detection.
IC design market slows; TSMC offers discounts on mature nodes
TSMC offers modest discounts on mature nodes as foundries cut prices; IC designers’ margins may be bottoming amid weak demand and inventory recovery.
Overview of Chip Packaging Technologies
Semiconductor packaging guide: wire bonding, flip-chip, FOWLP, 2D/2.5D/3D multi-die, interposers, EMIB and FOCoS trade-offs
Verification: the Heavy Burden in SoC Design
SoC design and verification: EDA tools, tapeout flows, power/security and scalability challenges, and gaps in China’s EDA.
Advanced Chip Design: Understanding Low Power
Explore low-power SoC design: techniques, dynamic vs static power, leakage, and subsystem impacts to extend battery life and reduce cost.
IC Design Flow and Tools Overview
Overview of IC design flow, covering front-end and back-end processes, tools, and key steps like HDL coding and physical verification.
Fundamentals of IC Layout
Learn N-well and CMOS layout fundamentals: N-well function, active areas, poly1 gates, diffusion, contacts, metals, vias and simple inverter layers.
Understanding SpyGlass CDC Flow for Chip Design
Learn CDC challenges, SpyGlass CDC analysis and best practices for detecting clock-domain crossing issues in complex SoC RTL designs.
EDA Expands Beyond Chip Design
EDA evolves beyond chip design, integrating AI/ML and multi-physics simulation for trillion-dollar markets in system design and digital twins.
Xilinx FPGA BGA: NSMD vs SMD Pad Differences
Guide to Xilinx BGA pitches (1.0, 0.92, 0.8, 0.5mm): PCB layer estimation, NSMD vs SMD pads, via planning and routing tips.
Understanding Power Consumption and Reduction Techniques
Explore chip power consumption, dynamic vs static power, and common digital IC techniques: clock/power gating, DVFS, multi-Vt and well biasing.
Differences Between Pre- and Post-Layout Simulation in IC Design
Compare pre-simulation vs post-simulation in IC design: functional vs timing verification, parasitics, placement, and simulation trade-offs.
Integrated On-Chip Technologies Explained
Explore electronic system integration: on chip (FEOL/BEOL), in package (SiP, RDL, TSV) and PCB integration from transistors to assemblies.