IC Chip Design with Copper Interconnects

Learn how copper interconnects, low-k dielectrics, SOI, and HKMG enable reliable, high-performance 32/28nm CMOS scaling and advanced lithography.

Overview of UVM for Digital IC Verification

Learn Coverage-Driven Verification (CDV) with UVM: testbench architecture, constrained-random testing, coverage collection, simulation and reuse.

Pipeline Design: Key Points

Pipeline design: temporal parallelism, stage partitioning, throughput vs. latency trade-offs, and backpressure handling for efficient hardware.

Yingnuoda Low-Power EDA Full-Flow Solution

Yingnuoda's low-power EDA tools (LPC, RPA, GPA) enable early RTL power estimation and optimization across the IC design flow.

Digital IC Front-End Design Flow and Tools

Gate-level netlist guide: synthesis, simulation, DFT, formal verification and STA for front-end/back-end design.

3D Perspective for Integrated Circuit Design

Explore Cubic IC 3D design: stacking storeys, EDA tool needs, LITS, EFV, manufacturing and thermal challenges for future ICs.

Fundamentals of IC Layout

Learn N-well and CMOS layout fundamentals: N-well function, active areas, poly1 gates, diffusion, contacts, metals, vias and simple inverter layers.

Basic TLM Communication for Digital IC Verification

Learn UVM TLM basics: building transactions, and using blocking put/get ports and exports for producer/consumer communication.

Metastability and Synchronizers in Chip Design

Learn metastability, MTBF, and synchronizer techniques for safe clock-domain crossings in multi-clock chip designs.

Understanding SpyGlass CDC Flow for Chip Design

Learn CDC challenges, SpyGlass CDC analysis and best practices for detecting clock-domain crossing issues in complex SoC RTL designs.

Verification: the Heavy Burden in SoC Design

SoC design and verification: EDA tools, tapeout flows, power/security and scalability challenges, and gaps in China’s EDA.

What Does Advanced-Process Chip Design Cost?

Why chip development costs may be lower than claimed: design simplification, advanced packaging, delayed node migration, software and EDA impacts.

Modern Electronic Integration: Scales and Dimensions

Explore electronic integration: scales from particles to systems, dimensions (2D-4D), and IC trends toward smaller scales and higher dimensions.

EMC: Electromagnetic Shielding Notes

Antenna models (loop, dipole), near/far-field radiation and shielding effectiveness: reflection, absorption, and practical EM shielding tips.

Register Write Protection Implementation for ICs

Explains hardware register write protection for PCIe SR-IOV doorbells using db_id/db_func mappings to enforce host isolation.

IC design market slows; TSMC offers discounts on mature nodes

TSMC offers modest discounts on mature nodes as foundries cut prices; IC designers’ margins may be bottoming amid weak demand and inventory recovery.

What IP and EDA Tools Do IC Designs Need?

Explore IC design challenges: 3DIC & chiplet interconnects, EDA/IP needs, edge processors, RISC-V evolution and China's EDA/IP integration.

Why the Semiconductor Industry Is Replacing FinFET

Explore how nanosheet (GAA) transistors and 3D chip stacking complement FinFET scaling, driving 2-3nm node advances and chiplet integration.

Difference Between Scan and BIST in Chip Test Design

Learn Scan and BIST DFT techniques for chip testability: scan paths, scan chains, LBIST/MBIST and built-in self-test benefits.

Challenges Facing the IC Design Industry

Weak semiconductor demand pressures driver ICs: analysts warn falling prices, shrinking margins and weak Q3 amid rising capacity and competition.