Understanding IEEE P802.3dj Ethernet Physical Layer
Analysis of IEEE 802.3dj and 212 Gb/s per-lane PHY: electrical validation, jitter measurement methodology, and implications for hyperscale data center interconnects.
Analysis of IEEE 802.3dj and 212 Gb/s per-lane PHY: electrical validation, jitter measurement methodology, and implications for hyperscale data center interconnects.
Technical overview of TVS diode protection for robotic systems: BMS short-circuit, motor drive and DC-DC surge schemes, plus signal interface ESD and EMC considerations.
MAX78002 evaluation kit overview: modular I/O for AI prototyping, supporting DVP/CSI cameras, I2S audio/mics, QWIIC expansion, power measurement and debug headers.
Overview of medical robots in digital health, covering surgical and microrobot applications, AI/ML-enabled perception, sensors, system architecture, and market trends.
LSG-SLAM: a stereo visual SLAM using 3D Gaussian splatting for large-scale outdoor reconstruction, improving tracking stability and mapping quality.
VPX361 8-channel RF transceiver using Xilinx Zynq UltraScale+ XCZU47DR SoC: eight 14-bit ADCs/DACs up to 6 GHz, 25 Gbps GTY backplane, DDR4/eMMC memory for radar and EW.
A concise technical review of AI history covering 10 pivotal milestones—from Dartmouth and perceptron to deep learning breakthroughs and the rise of large models.
Overview of intelligent video analytics (IVA), deployment scenarios and why edge computing and industrial computers enable low-latency, secure real-time video AI.
Technical guide to deploying PP-OCRv5 with Intel OpenVINO on a modular mini-PC: export Paddle models to ONNX, run CPU inference, and enable hardware-accelerated OCR.
Concise overview of embodied intelligence: definitions, categories (humanoid, wheeled, legged) and core technologies such as motion control and decision-making.
Deep Natural Anonymization (DNAT) replaces faces and plates with synthetic overlays, preserving age/gender for GDPR-compliant privacy and real-time 24 FPS edge processing.
Predictive maintenance and digital twin applications for AI-driven industrial process stability, enabling real-time parameter optimization and reduced downtime.
Run KleidiAI matmul microkernel on bare metal and compare Arm toolchains (AC6, GCC, ATfE) with cycle-count benchmarks and compiler optimization analysis.
Overview of FPGA applications in machine learning: accelerating neural network inference, hardware quantization, algorithm optimization, and efficiency for edge AI deployments.
TI EVM-ARC-AFE evaluation module: 4-channel analog front end for AI-based DC arc detection in solar systems, supports data labeling and C2000 controlCARDs.
Concise overview of numeric precision formats, FP64, FP32, FP16, TF32, BF16 and int8, comparing bit widths, accuracy trade-offs and use cases for AI training and inference.
Overview of the Analog Devices MAX78002 AI microcontroller - ultra-low-power dual-core MCU with power management and edge inference use cases for battery-powered devices.
Edge AI technical overview covering distributed architecture, model lightweighting, data preprocessing, and model deployment to edge devices for real-time inference.
Technical overview of FlashAttention v1–v3: memory-aware tiling, recomputation, and FP8 GPU optimizations that reduce HBM I/O and accelerate Transformer attention.
Overview of the MediaTek MT8391 (Genio 720) edge AI platform: 6 nm octa-core CPU, 10 TOPS NPU, dual ISPs, LPDDR5 support and multi-interface connectivity for AIoT devices.