Category:PCB PCB Stack-up

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PCB stack-up is an important factor in determining the EMC performance of a product, very effective in reducing radiation from the loops on the PCB.

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Guides for 10-Layer PCB Stack-up Reply 2017-02-19 14:44:43
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Bevis

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The following text is reproduced, with permission, from Part 5 of a 6-Part article on PCB Stackup by Henry W. Ott. The original article is available at http://www.hottconsultants.com/tips.html
A ten-layer board should be used when six routing layers are required. Ten-layer boards, therefore, usually have six signal layers and four planes. Having more than six signal layers on a ten-layer board is not recommended. Ten-layers is also the largest number of layers that can usually be conveniently fabricated in a 0.062" thick board. Occasionally you will see a twelve-layer board fabricated as a 0.062" thick board, but the number of fabricators capable of producing it are limited.
High layer count boards (ten +) require thin dielectrics (typically 0.006" or less on a 0.062" thick board) and therefore they automatically have tight coupling between layers. When properly stacked and routed they can meet all of our objectives and will have excellent EMC performance and signal integrity.
A very common and nearly ideal stack-up for a ten-layer board is shown in Figure 12. The reason that this stack-up has such good performance is the tight coupling of the signal and return planes, the shielding of the high-speed signal layers, the existence of multiple ground planes, as well as a tightly coupled power/ground plane pair in the center of the board. High-speed signals normally would be routed on the signal layers buried between planes (layers 3-4 and 7-8 in this case).
The common way to pair orthogonally routed signals in this configuration would be to pair layers 1 & 10 (carrying only low-frequency signals), as well as pairing layers 3 & 4, and layers 7 & 8 (both carrying high-speed signals). By paring signals in this manner, the planes on layers 2 and 9 provide shielding to the high-frequency signal traces on the inner layers. In addition the signals on layers 3 & 4 are isolated from the signals on layers 7 & 8 by the center power/ground plane pair. For example, high-speed clocks might be routed on one of these pairs, and high-speed address and data buses routed on the other pair. In this way the bus lines are protected, against being contaminated with clock noise, by the intervening planes.
This configuration satisfies all of the five original objectives.
Another possibility for routing orthogonal signals on the ten-layer board shown in Fig. 12 is to pair layers 1 & 3, layers 4 & 7, and layers 8 & 10. In the case of layer pairs 1 & 3 as well as 8 & 10, this has the advantage of routing orthogonal signals with reference to the same plane. The disadvantage, of course, is that if layers 1 and/or 10 have high frequency signals on them there is no inherent shielding provided by the PCB planes. Therefore, these signal layers should be placed very close to their adjacent plane (which occurs naturally in the case of a ten-layer board).
Each of the routing configurations discussed above has some advantages and some disadvantages, either can be made to provide good EMC and signal integrity performance if laid out carefully.
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Statement: This post is only the personal view of the author and does not represent the opinions of ALLPCB.com.

Bruno

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Remarkable.
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